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Smart memory hubs being proposed
Both AMD and Intel are proposing a separate but similar new approach to
memory interconnection design for the future. They are dubbing it smart memory hubs right now, but the details are a little sketchy. It involves putting some sort of intelligence right into the memory modules. http://www.eet.com/semi/news/OEG20030508S0023 The initial efforts are aimed at increasing memory density in servers. I'm not sure how exactly these hubs are supposed to be "smart". I also fail to see how adding another layer of circuitry in between the memory controller and memory itself would speed up memory accesses, since it adds another hop into the equation. However, perhaps these are the successors to the current SPD ROM that is implanted on every DIMM to describe its architecture to the memory controller on initialization? Perhaps these hubs send additional information that SPDs can't send by themselves? Yousuf Khan |
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