Marketing driving design

Looks like for the last few years Marketing was driving design philosophy at
intel and now they are paying for it. Intel designed CPUs the last few years
for the sole purpose of advertising bigger MHZ numbers over true performance
and high IPC, now prescott looks like a lame duck faltering under 4Ghz due
to the laws of physics, looks like Intel learned its lesson and dropped the
whole MHZ angle and will use Pentium M technology for 2005. So is intel
going to drop all Netburst nextyear? Its good to see them get back to
buisness though.

Hugo Drax wrote:
Looks like for the last few years Marketing was driving design
philosophy at intel and now they are paying for it. Intel designed
CPUs the last few years for the sole purpose of advertising bigger
MHZ numbers over true performance and high IPC, now prescott looks
like a lame duck faltering under 4Ghz due to the laws of physics,
looks like Intel learned its lesson and dropped the whole MHZ angle
and will use Pentium M technology for 2005. So is intel going to drop
all Netburst nextyear? Its good to see them get back to buisness
though.

Isn't the Netburst stuff what refers to their bus architecture? If so, then
Pentium M uses the same bus architecture as Pentium-M, doesn't it?

Yousuf Khan

Yousuf Khan wrote:

Isn't the Netburst stuff what refers to their bus architecture?

NetBurst is the micro-architecture.

c.f. the IA-32 Optimization Reference Manual.

Intel NetBurst microarchitecture is designed to achieve high
performance for both integer and floating-point computations
at high clock rates. It supports the following features:

o hyper-pipelined technology that enables high clock rates
and frequency headroom (up to 10 GHz)

o a high-performance, quad-pumped bus interface to the Intel
NetBurst microarchitecture system bus

o a rapid execution engine to reduce the latency of basic
integer instructions

o out-of-order speculative execution to enable parallelism

o superscalar issue to enable parallelism

o hardware register renaming to avoid register name space
limitations

o cache line sizes of 64 bytes

o hardware prefetch