Initial state of DDR RAM pins?

Hello all,

I was wondering if any one knows the state of the DDR RAM's
bidirectionnal pins upon power-on. And only upon power-on - no clk and
all other pins to ground. I am not interested in making the DDR RAM
operate properly, I just want to power it on in order to measure the
input pin leakage current.
I scoured the DDR's datasheet. I did not find if the bidirectionnal
pins are or aren't hi-z upon power-on.

All help is appreciated.

Kind regards,
-Roger.

In article .com, "Roger
Bourne" wrote:

Hello all,

I was wondering if any one knows the state of the DDR RAM's
bidirectionnal pins upon power-on. And only upon power-on - no clk and
all other pins to ground. I am not interested in making the DDR RAM
operate properly, I just want to power it on in order to measure the
input pin leakage current.
I scoured the DDR's datasheet. I did not find if the bidirectionnal
pins are or aren't hi-z upon power-on.

All help is appreciated.

Kind regards,
-Roger.

This text is extracted from a Micron DDR datasheet. Not from the
datasheet listed below, but just the first one I had on disk.

Initialization
DDR SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
Power must first be applied to VDD and VDDQ simultaneously,
and then to VREF (and to the system VTT). VTT
must be applied after VDDQ to avoid device latch-up,
which may cause permanent damage to the device.
VREF can be applied any time after VDDQ but is expected
to be nominally coincident with VTT. Except for CKE,
inputs are not recognized as valid until after VREF is
applied. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after VDD is applied. After CKE
passes through VIH, it will transition to a SSTL_2 signal
and remain as such until power is cycled. Maintaining
an LVCMOS LOW level on CKE during power-up is required
to ensure that the DQ and DQS outputs will be
in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.

That would suggest keeping CKE grounded while establishing
VDD/VDDQ, and then bringing up VREF/VTT, should place
DQ and DQS tristated.

The whole box of chocolates...
http://www.micron.com/products/dram/ddr/partlist.aspx
A 32Mx8 DDR400 TSOP...
http://www.micron.com/products/partd...MT46V32M8TG-5B
http://download.micron.com/pdf/datas...DDRx4x8x16.pdf

An analog simulation file of the input stage, would be as
meaningful as what you are trying to do. But the vast
majority of manufacturers, don't give real info, but
stuff like IBIS. I've only managed to get Spice decks
that were accurate for conditions outside the rails a
couple of times, and those days are over. (And you have
to be real careful, and check their handywork, because
usually the decks will be wrong the first time.) It is
too much fun for most companies, to hide behind their
IBIS pseudo info.

I think 10 minutes on the phone with an apps engineer,
would tell you as much as a whole week spent in the lab.
Perhaps you should be attacking the problem from the comfort
of your desk :-) Either have the apps engineer verify
the proper leakage measurement technique (if you don't
want to reveal your secret project), or describe to
him/her exactly what crazy scheme you have in mind.

Paul

..

I think 10 minutes on the phone with an apps engineer,
would tell you as much as a whole week spent in the lab.
Perhaps you should be attacking the problem from the comfort
of your desk :-) Either have the apps engineer verify
the proper leakage measurement technique (if you don't
want to reveal your secret project), or describe to
him/her exactly what crazy scheme you have in mind.



Great suggestions.
I just sent micron a list of technical questions. Unfortunately, I only
could find an [online form to complete]. I couldn't seem to find a
support phone number. That would have been to much to hope for :-( .

-Roger