Memory Speed

Provided the memory works on a motherboard/mainboard, is there any
reason why buying faster than needed (say DDR800 instead of DDR 667) is
not good to have it for a possible future use in a motherboard/mainboard
that can take advantage of the faster speeds?

Thanks in advance,

PB

In article , PB
wrote:

Provided the memory works on a motherboard/mainboard, is there any
reason why buying faster than needed (say DDR800 instead of DDR 667) is
not good to have it for a possible future use in a motherboard/mainboard
that can take advantage of the faster speeds?

Thanks in advance,

PB

The memory itself is supposed to be backward compatible. But
the question is whether the BIOS in all cases, will do the
right thing. The contents of the SPD declares the timing,
and it is up to the BIOS to read the timing and set up the
memory controller appropriately. If using a memory which
is faster than the max that your current motherboard
takes, the question is whether the BIOS will behave correctly.
I have read of cases, where a memory which is faster
than the motherboard takes, will result in a black screen
at startup. You really need to Google or try the private
forums, to see if your combo of slow motherboard and fast
memory, has been tried. (This is BIOS dependent and it
seems a lot of initial BIOS shipments, contain crappy
code for setting up memory.)

I would make sure your RAM vendor has some kind of
returns policy, in case you need to select a lower
clocking RAM, to get your current motherboard to work.

There is a non-standardized extension to the SPD timing
information format, which is apparently being presented
to JEDEC. This does not mean that JEDEC will accept it,
or that for the time being, more than a few Nvidia chipset
based boards will use the information, but this proposal
is intended to allow timing sets which are outside the
JEDEC official DIMM speeds to be recorded. I don't see
any harm in this, as long as BIOS which do not know
about EPP (enhanced performance profile), do not trip
over the extra information in the SPD EEPROM. I think
the "SLI" part of this announcement is less important,
since memory has no notion about how the rest of the
computer works, and could care less (but that is the
nature of marketing - some lies, a little substance).

(Announcement of EPP)
http://www.hexus.net/content/item.php?item=5622

While the Hexus article predicts that JEDEC will rubber
stamp this proposal, I wouldn't be so quick to proclaim
victory. There are many competing interests at JEDEC,
and no way to predict what will happen.

HTH,
Paul

Paul can I dl your brain and upload it into mine? :-P

Dan

Paul wrote:
In article , PB
wrote:

Provided the memory works on a motherboard/mainboard, is there any
reason why buying faster than needed (say DDR800 instead of DDR 667) is
not good to have it for a possible future use in a motherboard/mainboard
that can take advantage of the faster speeds?

Thanks in advance,

PB

The memory itself is supposed to be backward compatible. But
the question is whether the BIOS in all cases, will do the
right thing. The contents of the SPD declares the timing,
and it is up to the BIOS to read the timing and set up the
memory controller appropriately. If using a memory which
is faster than the max that your current motherboard
takes, the question is whether the BIOS will behave correctly.
I have read of cases, where a memory which is faster
than the motherboard takes, will result in a black screen
at startup. You really need to Google or try the private
forums, to see if your combo of slow motherboard and fast
memory, has been tried. (This is BIOS dependent and it
seems a lot of initial BIOS shipments, contain crappy
code for setting up memory.)

I would make sure your RAM vendor has some kind of
returns policy, in case you need to select a lower
clocking RAM, to get your current motherboard to work.

There is a non-standardized extension to the SPD timing
information format, which is apparently being presented
to JEDEC. This does not mean that JEDEC will accept it,
or that for the time being, more than a few Nvidia chipset
based boards will use the information, but this proposal
is intended to allow timing sets which are outside the
JEDEC official DIMM speeds to be recorded. I don't see
any harm in this, as long as BIOS which do not know
about EPP (enhanced performance profile), do not trip
over the extra information in the SPD EEPROM. I think
the "SLI" part of this announcement is less important,
since memory has no notion about how the rest of the
computer works, and could care less (but that is the
nature of marketing - some lies, a little substance).

(Announcement of EPP)
http://www.hexus.net/content/item.php?item=5622

While the Hexus article predicts that JEDEC will rubber
stamp this proposal, I wouldn't be so quick to proclaim
victory. There are many competing interests at JEDEC,
and no way to predict what will happen.

HTH,
Paul

In article , Mark
wrote:

You wrote in thusly:

The memory itself is supposed to be backward compatible. But the
question is whether the BIOS in all cases, will do the right thing.
The contents of the SPD declares the timing, and it is up to the BIOS
to read the timing and set up the memory controller appropriately. If
using a memory which is faster than the max that your current
motherboard takes, the question is whether the BIOS will behave
correctly. I have read of cases, where a memory which is faster than
the motherboard takes, will result in a black screen at startup. You
really need to Google or try the private forums, to see if your combo
of slow motherboard and fast memory, has been tried. (This is BIOS
dependent and it seems a lot of initial BIOS shipments, contain crappy
code for setting up memory.)

Would picking faster memory then the board needs also introduce clock
latencies? For example, memory equal to the board might produce 2223
timing, but faster memory might end up 4446 timing when used on the
same, slower, board. Thus the "faster" memory would actually be slower
than memory rated for the board.

The latency is determined by one of the timing numbers, times the
inverse of the clock frequency (called the clock period, typically in
nanoseconds). DDR400 CAS2 has the same latency as DDR2-800 CAS4.
The two effects exactly balance (clock period cut in half, latency
doubled). And so, a DDR2-800 CAS3 RAM is superior, in both bandwidth
and latency, to its DDR400 CAS2 predecessor.

DDR400 CAS2 - 400/2 = 200MHz clock == 5ns period, x CAS2 = 10ns
DDR2-800 CAS4 - 800/2 = 400MHz clock == 2.5ns period x CAS4 = 10ns
DDR2-800 CAS3 - 800/2 = 400MHz clock == 2.5ns period x CAS3 = 7.5ns

Also, while it doesn't always work out in all cases, in a general
sort of way, if you downclock a memory, the timing numbers change
in proportion. Inside the memory, everything in there lives in an
"analog world". The timing parameters inside the memory are
measured in nanoseconds, but not nice round nanoseconds. When
synchronized to the outside world, using the clock, those times
have to be rounded to the nearest clock edge.

The easiest way to illustrate, is with an example. People owning
old motherboards that could only take DDR266 memory, could buy
a stick of DDR400 CAS3 memory. If you take the ratio of 266/400,
that is 2/3. If you take 2/3rds of CAS3, you get CAS2. Thus,
you can buy DDR400 CAS3 and run it at DDR266 CAS2. That is the
general principle, but a principle without a lot of predictive
power - I still run into cases where the math predicts a certain
thing will work, and it does not. Some high clocking memories,
with timings like 3-4-4-8, do not make good low latency memory
when you turn them down, and I don't understand why that should
be. [ It is times like this, that we need a real memory chip
designer to pop into the news group... ]

Paul

"Paul" wrote in message ...
In article , Mark
wrote:

Would picking faster memory then the board needs also introduce clock
latencies? For example, memory equal to the board might produce 2223
timing, but faster memory might end up 4446 timing when used on the
same, slower, board. Thus the "faster" memory would actually be slower
than memory rated for the board.

The latency is determined by one of the timing numbers, times the
inverse of the clock frequency (called the clock period, typically in
nanoseconds). DDR400 CAS2 has the same latency as DDR2-800 CAS4.
The two effects exactly balance (clock period cut in half, latency
doubled). And so, a DDR2-800 CAS3 RAM is superior, in both bandwidth
and latency, to its DDR400 CAS2 predecessor.

DDR400 CAS2 - 400/2 = 200MHz clock == 5ns period, x CAS2 = 10ns
DDR2-800 CAS4 - 800/2 = 400MHz clock == 2.5ns period x CAS4 = 10ns
DDR2-800 CAS3 - 800/2 = 400MHz clock == 2.5ns period x CAS3 = 7.5ns

True, although with a few exceptions. E.g. some DDR memory
is perfectly capable of running CAS1.5 at 200MHz.

Also, you'll usually see better overall system performance by
focusing on clock speed rather than latency. If Mark's faster
memory is capable of higher clock speeds, he shouldn't worry
if he needs to loosen his timings a bit to accomplish it.

Also, while it doesn't always work out in all cases, in a general
sort of way, if you downclock a memory, the timing numbers change
in proportion. Inside the memory, everything in there lives in an
"analog world". The timing parameters inside the memory are
measured in nanoseconds, but not nice round nanoseconds. When
synchronized to the outside world, using the clock, those times
have to be rounded to the nearest clock edge.

The easiest way to illustrate, is with an example. People owning
old motherboards that could only take DDR266 memory, could buy
a stick of DDR400 CAS3 memory. If you take the ratio of 266/400,
that is 2/3. If you take 2/3rds of CAS3, you get CAS2. Thus,
you can buy DDR400 CAS3 and run it at DDR266 CAS2. That is the
general principle, but a principle without a lot of predictive
power - I still run into cases where the math predicts a certain
thing will work, and it does not. Some high clocking memories,
with timings like 3-4-4-8, do not make good low latency memory
when you turn them down, and I don't understand why that should be.

It's two separate design issues. Memory chips can be built
for speed, low latency or a compromise of both. Which is
preferable depends entirely on the application. Look at
video card memory as one example.