AMD has no plans to push BTX boards

http://www.theinquirer.net/?article=19969

ykhan wrote:
http://www.theinquirer.net/?article=19969

No surprise there. BTX is Intel's answer to all the
heat their P4's produce. AMD's solution is simply
to not make so much heat in the first place. And the
differences are very large - about a 45 to 50 W
difference between a 2.2 GHz Athlon FX and a 3.4 GHz P4.

Can't quite understand why Intel wouldn't simply kill
off the P4 and use the Pentium M to compete with AMD.
Comparable clock-for-clock performance using 40% as much
power. Put an on-chip memory controller into Dothan
and give it the 64 bit x86-64 extensions and it would
probably be a real Opteron killer.

Rob Stow wrote in message news:bMcrd.383503$Pl.276907@pd7tw1no...

Can't quite understand why Intel wouldn't simply kill
off the P4 and use the Pentium M to compete with AMD.
Comparable clock-for-clock performance using 40% as much
power. Put an on-chip memory controller into Dothan
and give it the 64 bit x86-64 extensions and it would
probably be a real Opteron killer.

On-chip RAM controller is apparently not going to be ready till 2007,
last I read. Hell, it took AMD about two years to integrate the memory
controller, otherwise Opteron/Athlon 64 would've been out about two
years ago. Even with the memory controller, P-M still wouldn't have
the Hypertransport, so no answer to Opteron yet, but it might be a
compelling competitor to Athlon 64.

Yousuf Khan

On Wed, 01 Dec 2004 06:36:20 -0800, ykhan wrote:

Rob Stow wrote in message news:bMcrd.383503$Pl.276907@pd7tw1no...

Can't quite understand why Intel wouldn't simply kill
off the P4 and use the Pentium M to compete with AMD.
Comparable clock-for-clock performance using 40% as much
power. Put an on-chip memory controller into Dothan
and give it the 64 bit x86-64 extensions and it would
probably be a real Opteron killer.

On-chip RAM controller is apparently not going to be ready till 2007,

I find this simply *amazing*!!

last I read. Hell, it took AMD about two years to integrate the memory
controller,

I highly doubt that took all of two years. Come on, Yousuf! It's a damned
*memory controller*! What? a few tens of thousand gates and a few I/O?

OTOH, I gotta admit that I have no clue why we haven't had this for
*years*. Bandwith is nice, but latency is *king*.

otherwise Opteron/Athlon 64 would've been out about two
years ago. Even with the memory controller, P-M still wouldn't have
the Hypertransport, so no answer to Opteron yet, but it might be a
compelling competitor to Athlon 64.

I don't see HT as being a lynchpin. Indeed the only reason it's
interesting is because of the integrated memory controller.

--
Keith

On 1 Dec 2004 06:36:20 -0800, (ykhan) wrote:

Rob Stow wrote in message news:bMcrd.383503$Pl.276907@pd7tw1no...

Can't quite understand why Intel wouldn't simply kill
off the P4 and use the Pentium M to compete with AMD.
Comparable clock-for-clock performance using 40% as much
power. Put an on-chip memory controller into Dothan
and give it the 64 bit x86-64 extensions and it would
probably be a real Opteron killer.

On-chip RAM controller is apparently not going to be ready till 2007,
last I read.

If that is indeed the case, what in the hell is taking Intel so
long?!?! It's not like they don't know how to build a memory
controller! Certainly it seems that integrating the memory controller
on the CPU die has been proven to be the way forward. Intel is now
pretty much the only company that has not done so yet.

Hell, it took AMD about two years to integrate the memory
controller, otherwise Opteron/Athlon 64 would've been out about two
years ago.

Err, the Opteron was out more than a year and a half ago. Not quite
two years yet, but it's getting pretty close.

Even with the memory controller, P-M still wouldn't have
the Hypertransport, so no answer to Opteron yet, but it might be a
compelling competitor to Athlon 64.

Once Intel finally gets around to integrating a memory controller
on-die, it no longer makes sense to have a traditional processor bus,
so I would imagine that they'll have a hypertransport-like solution.
I'm guessing that they won't use Hypertransport itself, but probably
something that is very similar. They've already got their
"Accelerated Hub Architecture" bus and PCI-Express as potential
candidates to base such a design off of.

-------------
Tony Hill
hilla underscore 20 at yahoo dot ca

On Thu, 02 Dec 2004 08:24:07 -0500, Tony Hill
wrote:

On 1 Dec 2004 06:36:20 -0800, (ykhan) wrote:

Rob Stow wrote in message news:bMcrd.383503$Pl.276907@pd7tw1no...

Can't quite understand why Intel wouldn't simply kill
off the P4 and use the Pentium M to compete with AMD.
Comparable clock-for-clock performance using 40% as much
power. Put an on-chip memory controller into Dothan
and give it the 64 bit x86-64 extensions and it would
probably be a real Opteron killer.

On-chip RAM controller is apparently not going to be ready till 2007,
last I read.

If that is indeed the case, what in the hell is taking Intel so
long?!?! It's not like they don't know how to build a memory
controller!

Hmmm, could it be that the road-map has become more important than the err,
road? Of course it would also involve a generous helping of crow, I'd say.
It's certainly going to be interesting to see how they spin it? If this is
how they arrive at the unified Itanium/x86 system architecture, it seems a
bit flat to me. :-)

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??

keith wrote in message .. .
On Wed, 01 Dec 2004 06:36:20 -0800, ykhan wrote:
On-chip RAM controller is apparently not going to be ready till 2007,

I find this simply *amazing*!!

Let's face it, we totally forget how much headache AMD went through,
designing all of these things quietly in the wilderness. It took a lot
of PR lumps from Intel for not responding to every little Pentium 4
speed increment or feature with an equivalent Athlon XP feature or
increment. It's now AMD's turn to laugh -- it's built up a huge lead
on Intel.

last I read. Hell, it took AMD about two years to integrate the memory
controller,

I highly doubt that took all of two years. Come on, Yousuf! It's a damned
*memory controller*! What? a few tens of thousand gates and a few I/O?

Well, I'm sure the original design was done fairly quickly, but then
they probably had a lot of tweaking and retuning, testing and
validation to do. Testing it out on low-quality ram, etc.

Plus, this type of memory controller has never been done before,
something operating at the speed of the processor that is. All
chipset-based ram controllers were operating in the 100's of Mhz
range, this one has to operate at several Ghz.

I don't see HT as being a lynchpin. Indeed the only reason it's
interesting is because of the integrated memory controller.

Not so much on a single-processor Athlon 64, sure, but quite a
lynchpin in a multiprocessor Opteron setting.

Yousuf Khan

Tony Hill wrote in message . ..
On-chip RAM controller is apparently not going to be ready till 2007,
last I read.

If that is indeed the case, what in the hell is taking Intel so
long?!?! It's not like they don't know how to build a memory
controller! Certainly it seems that integrating the memory controller
on the CPU die has been proven to be the way forward. Intel is now
pretty much the only company that has not done so yet.

Well, a memory controller operating out of a chipset only has to
operate at several hundred Mhz. One operating out of a CPU will be
operating at several Ghz (especially if it's inside a P4 which was
designed to do nothing but Ghz).

Hell, it took AMD about two years to integrate the memory
controller, otherwise Opteron/Athlon 64 would've been out about two
years ago.

Err, the Opteron was out more than a year and a half ago. Not quite
two years yet, but it's getting pretty close.

I was talking about the amount of time that the design spent being
implemented prior to release.

Even with the memory controller, P-M still wouldn't have
the Hypertransport, so no answer to Opteron yet, but it might be a
compelling competitor to Athlon 64.

Once Intel finally gets around to integrating a memory controller
on-die, it no longer makes sense to have a traditional processor bus,
so I would imagine that they'll have a hypertransport-like solution.
I'm guessing that they won't use Hypertransport itself, but probably
something that is very similar. They've already got their
"Accelerated Hub Architecture" bus and PCI-Express as potential
candidates to base such a design off of.

I was thinking not so much about I/O demands as I was for
multiprocessor cache-coherency.

Yousuf Khan

George Macdonald wrote in message . ..
Hmmm, could it be that the road-map has become more important than the err,
road? Of course it would also involve a generous helping of crow, I'd say.
It's certainly going to be interesting to see how they spin it? If this is
how they arrive at the unified Itanium/x86 system architecture, it seems a
bit flat to me. :-)

Isn't the Itanium bus supposed to be yet another shared bus too, just
like Pentium's bus? How exactly will it be able to compete against
Hypertransport?

Yousuf Khan

On Thu, 02 Dec 2004 15:46:19 -0800, ykhan wrote:

keith wrote in message .. .
On Wed, 01 Dec 2004 06:36:20 -0800, ykhan wrote:
On-chip RAM controller is apparently not going to be ready till 2007,

I find this simply *amazing*!!

Let's face it, we totally forget how much headache AMD went through,
designing all of these things quietly in the wilderness. It took a lot
of PR lumps from Intel for not responding to every little Pentium 4
speed increment or feature with an equivalent Athlon XP feature or
increment. It's now AMD's turn to laugh -- it's built up a huge lead
on Intel.

I look at it entirely differently. Intel *has* DRAM controller expertise.
They *have* the tools they need. Where are they? Intel has more than
three engineers in a basement, eating mold, somehwere. Five years to port
a DRAM controller?

last I read. Hell, it took AMD about two years to integrate the
memory controller,

I highly doubt that took all of two years. Come on, Yousuf! It's a
damned *memory controller*! What? a few tens of thousand gates and a
few I/O?

Well, I'm sure the original design was done fairly quickly, but then
they probably had a lot of tweaking and retuning, testing and validation
to do. Testing it out on low-quality ram, etc.

Oh, come on! They *have* that expertise. Thre is something fishy here
(likely, stinky pointy-haired fish). NIH is a bitch!

Plus, this type of memory controller has never been done before,
something operating at the speed of the processor that is. All
chipset-based ram controllers were operating in the 100's of Mhz range,
this one has to operate at several Ghz.

Oh crap, Yousuf! The FSB doesn't run at the core frequency either. I
don't seeee this as any issue at all. Processor technology is the
bleeding edge.

I don't see HT as being a lynchpin. Indeed the only reason it's
interesting is because of the integrated memory controller.

Not so much on a single-processor Athlon 64, sure, but quite a lynchpin
in a multiprocessor Opteron setting.

It would be a rather crappy connection without the integrated memory
controller. That is, a northbridge hanging off HT would be a disaster.

--
Keith