Multi-core and memory

"Chris Thomasson" wrote in message
. ..

"MitchAlsup" wrote in message
...
On May 22, 12:23 am, "Chris Thomasson" wrote:
[...]
IMVHO, drastically reducing the physical distance between the chip and
its
local memory can be very important factor wrt scalability concerns. It
should be ideal to merge the chip and a couple of GB of memory into a
single
unit.

Intra-CPU to local memory communication would use shared memory, and
inter-CPU and remote memory communication would use message passing. It
seems the scheme could be made to work... What am I missing?

Heat disipation. One could, in principle, design a DRAM daughtercard
that had an Opteron/Barcelona socket in the middle, ranks of DRAMs to
the left and right, and HT links through the pins. Dealing with the
100Watts of power at the center would make the spacing between
daughter cards pretty large, and cooling a little on the difficult
side.

BUT it is possible today, if you wanted to try and make a go of it.

Do you know of _any_ venture capitalists who might be even remotely
interested in reducing the physical distance between processing elements and
their local/regional memory source(s)? My cousins sister is good friends
with a guy from Google (his first name is Ray). Should I ask him what he
thinks? Would I be wasting his time???? He spends his some of hard earned
money in the form of donations to the South Lake Tahoe Basin and Douglas
County Region of Nevada. This is real. I have several Ideas, but I DO NOT
like to WASTE peoples TIME! Any advise Sir?!

;^/




Humm. I was thinking that a clever mixture of high-end liquid cooling
systems and fans might be able to help things out in this specific problem
domain.

Are there any integral caveats wrt state-of-the-art liquid and fan
intergraded cooling systems?

"Chris Thomasson" wrote in message
...

"Chris Thomasson" wrote in message
. ..

"MitchAlsup" wrote in message
...
On May 22, 12:23 am, "Chris Thomasson" wrote:
[...]
IMVHO, drastically reducing the physical distance between the chip
and its
local memory can be very important factor wrt scalability concerns.
It
should be ideal to merge the chip and a couple of GB of memory into
a single
unit.

Intra-CPU to local memory communication would use shared memory,
and
inter-CPU and remote memory communication would use message
passing. It
seems the scheme could be made to work... What am I missing?

Heat disipation. One could, in principle, design a DRAM daughtercard
that had an Opteron/Barcelona socket in the middle, ranks of DRAMs to
the left and right, and HT links through the pins. Dealing with the
100Watts of power at the center would make the spacing between
daughter cards pretty large, and cooling a little on the difficult
side.

BUT it is possible today, if you wanted to try and make a go of it.

Do you know of _any_ venture capitalists who might be even remotely
interested in reducing the physical distance between processing
elements and their local/regional memory source(s)? My cousins sister
is good friends with a guy from Google (his first name is Ray). Should
I ask him what he thinks? Would I be wasting his time???? He spends his
some of hard earned money in the form of donations to the South Lake
Tahoe Basin and Douglas County Region of Nevada. This is real. I have
several Ideas, but I DO NOT like to WASTE peoples TIME! Any advise
Sir?!

;^/




Humm. I was thinking that a clever mixture of high-end liquid cooling
systems and fans might be able to help things out in this specific
problem domain.

Are there any integral caveats wrt state-of-the-art liquid and fan
intergraded cooling systems?

Perhaps you ought to review IBM Mainframe designs, high end Pseries
designs, and Blue Gene/L and BlueGene/P.

or are you guys just being snarky and I didn't notice?

del

On May 21, 11:23 pm, "Chris Thomasson" wrote:
"Rui Pedro Mendes Salgueiro" wrote in ...

Hello

Would it make sense to have multiple memory interfaces in multi-core CPUs
?
Have Intel or AMD announced plans to have such a thing ?

[...]

I have always wondered why a multi-core CPU could not be
__directly_integrated__ into a memory card. IMHO, a 2GB mem-card should be
able to physically integrate with one or two multi-core CPU's. The memory
which resides on the same card as the CPU(s) could be accessed using a cache
coherent shared memory model. If one card needs to communicate with another,
then a message-passing interface would be utilized. Think of a single
desktop sized system that has 8 2GB cards with two 64-core CPU's per-card.
That's 16GB of total distributed memory running on 1024 cores...

Does anybody know of any experimental projects that are trying to accomplish
something even vaguely similar?

Of course, the chip vendor would need to be the memory vendor as well...
Humm...

IMVHO, drastically reducing the physical distance between the chip and its
local memory can be very important factor wrt scalability concerns. It
should be ideal to merge the chip and a couple of GB of memory into a single
unit.

Intra-CPU to local memory communication would use shared memory, and
inter-CPU and remote memory communication would use message passing. It
seems the scheme could be made to work... What am I missing?

With this type of setup, it seems like each card could be running a separate
operating system that is physically isolated from the other cards in the
system. Their only communication medium would be message passing. OS(a)
running on Card(a) could communicate with OS(b) running on Card(b) using
MPI. Card(a) intra-comm could use shared memory. This sure seems like it
would scale. Adding extra cards would not seem to be a problem. They might
even be able to be hot-swappable. Humm...

The programming model would be something like:

http://groups.google.com/group/comp....dbf634f491f46b

http://groups.google.com/group/comp....5eeaecd0e69aed

Basically, intra-node communication is analogous to inter-card comms, and
inter-node comms would be similar to inter-card comm...

Any thoughts?

Are you talking about processor in memory (PIM) and intelligent RAM
(IRAM)? There are many academic projects which have implemented/
proposed what you are talking about.

"Neal" wrote in message
...
On May 21, 11:23 pm, "Chris Thomasson" wrote:
"Rui Pedro Mendes Salgueiro" wrote in
...

Hello

Would it make sense to have multiple memory interfaces in multi-core
CPUs
?
Have Intel or AMD announced plans to have such a thing ?

[...]

I have always wondered why a multi-core CPU could not be
__directly_integrated__ into a memory card. IMHO, a 2GB mem-card should
be
able to physically integrate with one or two multi-core CPU's. The memory
which resides on the same card as the CPU(s) could be accessed using a
cache
coherent shared memory model. If one card needs to communicate with
another,
then a message-passing interface would be utilized. Think of a single
desktop sized system that has 8 2GB cards with two 64-core CPU's
per-card.
That's 16GB of total distributed memory running on 1024 cores...

Does anybody know of any experimental projects that are trying to
accomplish
something even vaguely similar?

Of course, the chip vendor would need to be the memory vendor as well...
Humm...

IMVHO, drastically reducing the physical distance between the chip and
its
local memory can be very important factor wrt scalability concerns. It
should be ideal to merge the chip and a couple of GB of memory into a
single
unit.

Intra-CPU to local memory communication would use shared memory, and
inter-CPU and remote memory communication would use message passing. It
seems the scheme could be made to work... What am I missing?

With this type of setup, it seems like each card could be running a
separate
operating system that is physically isolated from the other cards in the
system. Their only communication medium would be message passing. OS(a)
running on Card(a) could communicate with OS(b) running on Card(b) using
MPI. Card(a) intra-comm could use shared memory. This sure seems like it
would scale. Adding extra cards would not seem to be a problem. They
might
even be able to be hot-swappable. Humm...

The programming model would be something like:

http://groups.google.com/group/comp....dbf634f491f46b

http://groups.google.com/group/comp....5eeaecd0e69aed

Basically, intra-node communication is analogous to inter-card comms, and
inter-node comms would be similar to inter-card comm...

Any thoughts?

Are you talking about processor in memory (PIM) and intelligent RAM
(IRAM)? There are many academic projects which have implemented/
proposed what you are talking about.

I am talking about integrating a multi-core processor with a 2GB of DDR3
memory in a single pluggable card. Think if one could cram a N-core
processor directly into the following card:

http://www.corsair.com/products/dominator.aspx

I was just wondering of that could be possible, or if its a pipe-dream...

:^o

On Jun 6, 4:26 pm, "Chris Thomasson" wrote:
"Neal" wrote in message

...



On May 21, 11:23 pm, "Chris Thomasson" wrote:
"Rui Pedro Mendes Salgueiro" wrote in
...

Hello

Would it make sense to have multiple memory interfaces in multi-core
CPUs
?
Have Intel or AMD announced plans to have such a thing ?

[...]

I have always wondered why a multi-core CPU could not be
__directly_integrated__ into a memory card. IMHO, a 2GB mem-card should
be
able to physically integrate with one or two multi-core CPU's. The memory
which resides on the same card as the CPU(s) could be accessed using a
cache
coherent shared memory model. If one card needs to communicate with
another,
then a message-passing interface would be utilized. Think of a single
desktop sized system that has 8 2GB cards with two 64-core CPU's
per-card.
That's 16GB of total distributed memory running on 1024 cores...

Does anybody know of any experimental projects that are trying to
accomplish
something even vaguely similar?

Of course, the chip vendor would need to be the memory vendor as well...
Humm...

IMVHO, drastically reducing the physical distance between the chip and
its
local memory can be very important factor wrt scalability concerns. It
should be ideal to merge the chip and a couple of GB of memory into a
single
unit.

Intra-CPU to local memory communication would use shared memory, and
inter-CPU and remote memory communication would use message passing. It
seems the scheme could be made to work... What am I missing?

With this type of setup, it seems like each card could be running a
separate
operating system that is physically isolated from the other cards in the
system. Their only communication medium would be message passing. OS(a)
running on Card(a) could communicate with OS(b) running on Card(b) using
MPI. Card(a) intra-comm could use shared memory. This sure seems like it
would scale. Adding extra cards would not seem to be a problem. They
might
even be able to be hot-swappable. Humm...

The programming model would be something like:

http://groups.google.com/group/comp....dbf634f491f46b

http://groups.google.com/group/comp....5eeaecd0e69aed

Basically, intra-node communication is analogous to inter-card comms, and
inter-node comms would be similar to inter-card comm...

Any thoughts?

Are you talking about processor in memory (PIM) and intelligent RAM
(IRAM)? There are many academic projects which have implemented/
proposed what you are talking about.

I am talking about integrating a multi-core processor with a 2GB of DDR3
memory in a single pluggable card. Think if one could cram a N-core
processor directly into the following card:

http://www.corsair.com/products/dominator.aspx

I was just wondering of that could be possible, or if its a pipe-dream...

:^o

You wouldn't solve the pin bandwidth problem by doing this. Meaning,
that bandwidth across DRAM-CPU wouldn't be improved. What you would
have to do is either place the DRAM and CPU on the same die, or
connect the two die together either via a multi-chip module or die
stacking (and then place in the same package. There are of course
problems with doing this which I'm not discussing here.

In short, you can certainly gain what you are talking about in theory,
but at the chip level rather than the board level.

Neal

On Jun 6, 7:50 pm, Neal wrote:

What you would
have to do is either place the DRAM and CPU on the same die, or
connect the two die together either via a multi-chip module or die
stacking (and then place in the same package.

like this:

http://www.eetimes.com/showArticle.j...leID=208402316

slashdotted today.

Robert.

In comp.arch Chris Thomasson wrote:
I am talking about integrating a multi-core processor with a 2GB of DDR3
memory in a single pluggable card.

I think the biggest problem you'd have with that would be thermal if
you want all that in a DIMM-like form factor. If you need 30 in^3 of
thermal management infrastructure for each one then you might as well
have discrete processors and separate memory maybe.

I was just wondering of that could be possible, or if its a pipe-dream...

A heat-pipe-dream.

G.

"Robert Myers" wrote in message
...
On Jun 6, 7:50 pm, Neal wrote:

What you would
have to do is either place the DRAM and CPU on the same die, or
connect the two die together either via a multi-chip module or die
stacking (and then place in the same package.

like this:

http://www.eetimes.com/showArticle.j...leID=208402316

slashdotted today.

Kind of sounds vaguely similar to something like:

http://groups.google.com/group/comp....fd728c57a75d9a

hi this thing does have its bad sides
but the good ones are way better

"Chris Thomasson" wrote in message
. ..
"Robert Myers" wrote in message
...
On Jun 6, 7:50 pm, Neal wrote:

What you would
have to do is either place the DRAM and CPU on the same die, or
connect the two die together either via a multi-chip module or die
stacking (and then place in the same package.

like this:

http://www.eetimes.com/showArticle.j...leID=208402316

slashdotted today.

Kind of sounds vaguely similar to something like:

http://groups.google.com/group/comp....fd728c57a75d9a

Humm...... When you get some _really_ free time, go ahead and spend a few
minutes thinking along the line of:

http://groups.google.com/group/comp....74295430deb430
(Please read entire thread...)



WOW! Nano/Bio-Gates... Very Slick! Some genius actually created workable
gates out of several molecules! :^O




Any Thoughts?