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A new computer architecture
Dear All:
Please visit my site at: http://mysite.verizon.net/~vze26krk/CPM.html There, I will discuss the end of Moore's law, and a new computer architecture with I have proposed in 2003. Here is the abstract of my paper: "A novel memory with limited processing power and internal connectivity at each element is proposed. This memory carries out parallel processing within itself. Many common algorithms using this memory are discussed. For an array of N items, it reduces the total instruction cycle count of universal operations such as insertion and match finding to ~ 1, local operations such as filtering and pattern recognition to ~ local operation size, and global operations such as sum and sorting to ~ sqrt(N). Particularly, it eliminates most streaming activities for data processing purpose on the data bus. Yet it remains general purposed, easy to use, pin compatible with conventional memory, and practical for implementation. In addition, some new designs, such as all-line decoder, general decoder, parallel shifter, parallel comparator, parallel adder and parallel divider, are presented." Please drop a line to my email at: Regards, Chengpu Wang |
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On Fri, 04 Feb 2005 01:18:03 GMT, "Yingxia Wang"
wrote: There, I will discuss the end of Moore's law, and a new computer architecture with I have proposed in 2003. Here is the abstract of my paper: "A novel memory with limited processing power and internal connectivity at each element is proposed. This memory carries out parallel processing within itself. Many common algorithms using this memory are discussed. For an array of N items, it reduces the total instruction cycle count of universal operations such as insertion and match finding to ~ 1, local operations such as filtering and pattern recognition to ~ local operation size, and global operations such as sum and sorting to ~ sqrt(N). Particularly, it eliminates most streaming activities for data processing purpose on the data bus. Yet it remains general purposed, easy to use, pin compatible with conventional memory, and practical for implementation. In addition, some new designs, such as all-line decoder, general decoder, parallel shifter, parallel comparator, parallel adder and parallel divider, are presented." Err... that sounds stunningly like my 2nd year CS/EE degree project on VSLI design at Edinburgh University, circa 1983. The processing I was putting into the memory was simpler (hey, it was *1983*), but tuned to specific applications (string and set operations, as I recall). The snag is the software. Until you get a mechanism to more-or-less transparently offload the special-purpose processing without re-writing the app, it's nothing more than a curiosity. (see the speed of adoption of the "new" instructions in Intel and AMD processors -- SSE, etc. -- and the rationale for CPUs with hyperthreading...) Malc. |
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