Another Intel vs AMD Comparison

Raymond wrote:

"David Maynard" wrote in message
...


leaves through your sink only, from the top of the processor.

Oh, please do show me the calculations of all this massive heat flux
leaving by other means and how much more or less it is for each package.
And while you're at it explain why the two identical processors, made on
the same process, in identical FC-PGA packages have different thermal
output numbers.


Because not only do different packages conduct different amounts of heat,
the number of pins themselves also can have a small effect on power consumed.
That's another reason for the small difference, besides others, on same die,
same process, same transistor count, same architecture, same clock. No one
said it was huge, just big enough to screw up your silly comparison.

For heaven's sake, man, at least TRY to make sense. It's the same number of
pins, even between the two packages, and there's absolutely NOTHING
different between the two in the exact same package, except the power.

You want huge? Consider the 150+% power difference between a clock
normalized Dothan and an equivalent Prescott, for which you have no way of
accounting, except to throw your hands up in the air and say,
"oh there are too many factors, I give up", when it's very obvious that pipeline
depth is the main variant and the most likely culprit.

It's 'obvious' to you, the oblivious, just as it was 'obvious' to caveman
that thunder and lightning came from the gods because they knew of nothing
else.


But hey, you still think latches and pipelines are a near zero factor in power
consumption. So let's see:

This is the equation relating pipelines, latches and power, from Srinivasan et al :

Total Power = (((degree of clock gating) * (processor frequency) * (dynamic power factor
/latch)) + (leakage power factor/latch)) * (total latches)

Where, total latches = latches per pipeline stage * number of pipelines

And now you've got nothing but the pipeline latches consuming power, eh?

Do latches and pipelines seem like a "a spit causing a flood during a tsunami" type
of factor to you, still?!

Compared to the 90mm leakage problem, yes, because it is.

"David Maynard" wrote in message
...
But hey, you still think latches and pipelines are a near zero factor in power
consumption. So let's see:

This is the equation relating pipelines, latches and power, from Srinivasan et al :

Total Power = (((degree of clock gating) * (processor frequency) * (dynamic power
factor
/latch)) + (leakage power factor/latch)) * (total latches)

Where, total latches = latches per pipeline stage * number of pipelines

And now you've got nothing but the pipeline latches consuming power, eh?

Not MY equation! Same equation has been used in other studies
about power and performance, it's widely cited. For example:

http://www.microarch.org/micro36/htm...timumPower.pdf
Equation #3

Send the author's an e-mail telling them they're oblivious and not
to make such a big deal about "a spit during a tsunami". G

Raymond wrote:
"David Maynard" wrote in message
...
But hey, you still think latches and pipelines are a near zero
factor in power consumption. So let's see:

This is the equation relating pipelines, latches and power, from
Srinivasan et al :

Total Power = (((degree of clock gating) * (processor frequency)
* (dynamic power factor /latch)) + (leakage power factor/latch)) *
(total latches)

Where, total latches = latches per pipeline stage * number of
pipelines

And now you've got nothing but the pipeline latches consuming power,
eh?

Not MY equation! Same equation has been used in other studies
about power and performance, it's widely cited. For example:

http://www.microarch.org/micro36/htm...timumPower.pdf
Equation #3

Send the author's an e-mail telling them they're oblivious and not
to make such a big deal about "a spit during a tsunami". G

LOL. Just for the hell of it I've gone back over this thread to see you
changing your tune by the day and I see another very interesting trend.
Often a half-dozen of your "facts" will be refuted in one post and if there
is *one* that you feel you can defend you try it. You ignore the other
corrections as they're right.

Some posts that were irrefutable and proved you wrong you've ignored all
together.

So far the score is:

Raymond: 0
Rest of NG: 16

It would seem that Raymond does in fact have a few points that are true and
correct but, if you follow the thread back, you'll see that, several posts
back, he was arguing *against* them. Once it becomes obvious to even him
that he is holding an untenable position he does an about-face without even
blinking, taking the other persons point as his own. He is getting deeper
and deeper into finding corroborating evidence that support his wildly
innacurate statements. He seems to forget that, for every "expert". there is
and equal and opposite "expert". He must be spending a lot of time on this,
it's obviously very important to him to actually get something right. Sorry,
correction: To prove someone wrong. It's a negative thing he's doing, not
positive.

Really quite interesting study of a personallity. There are probably
psychologists out there that would find this interesting. Or not.
--
~Shaun~

"~misfit~" wrote in message ...
LOL. Just for the hell of it I've gone back over this thread to see you
changing your tune by the day and I see another very interesting trend.
Often a half-dozen of your "facts" will be refuted in one post and if there
is *one* that you feel you can defend you try it. You ignore the other
corrections as they're right.

Some posts that were irrefutable and proved you wrong you've ignored all
together.

So far the score is:

Raymond: 0
Rest of NG: 16

It would seem that Raymond does in fact have a few points that are true and
correct but, if you follow the thread back, you'll see that, several posts
back, he was arguing *against* them. Once it becomes obvious to even him
that he is holding an untenable position he does an about-face without even
blinking, taking the other persons point as his own. He is getting deeper
and deeper into finding corroborating evidence that support his wildly
innacurate statements. He seems to forget that, for every "expert". there is
and equal and opposite "expert". He must be spending a lot of time on this,
it's obviously very important to him to actually get something right. Sorry,
correction: To prove someone wrong. It's a negative thing he's doing, not
positive.

Really quite interesting study of a personallity. There are probably
psychologists out there that would find this interesting. Or not.

I've not done "an about face" about a single thing here. What I'm sure
you're referring to is my position that you can't keep increasing
clocks using deeper pipelines. My position on that is the
same. You can't! You say it's only because of thermal issues that
you can't. Well I just showed that thermal issue are related to
pipeline depth. So where is the about face there?

The only thing I will admit is that if you have a processor that
uses a shallower than optimal pipelines, you can increase the clock
with deeper pipelines. But that's not the case with the Pentium 4.
Never was! I don't believe that the Pentium 4 is higher clocked because
of pipeline depth, never did, and still don't.

Raymond wrote:

"David Maynard" wrote in message
...

But hey, you still think latches and pipelines are a near zero factor in power
consumption. So let's see:

This is the equation relating pipelines, latches and power, from Srinivasan et al :

Total Power = (((degree of clock gating) * (processor frequency) *(dynamic power

factor

/latch)) + (leakage power factor/latch)) * (total latches)

Where, total latches = latches per pipeline stage * number of pipelines

And now you've got nothing but the pipeline latches consuming power, eh?


Not MY equation! Same equation has been used in other studies
about power and performance, it's widely cited. For example:

http://www.microarch.org/micro36/htm...timumPower.pdf
Equation #3

Send the author's an e-mail telling them they're oblivious and not
to make such a big deal about "a spit during a tsunami". G

I don't need to email them because they know what they're talking about.
It's you who don't and misread it, not to mention misapply it to the
discussion.

The paper does not say pipeline length causes leakage, as you erroneously
claimed, it studies a new definition for 'optimum' pipeline depth by adding
power consumption, rather than just raw processing, to the criteria for
'optimum'. In particular, BIPSm/W. That assumes one actually 'cares' about
optimizing power consumption, an assumption which might vary depending on
whether one is running a notebook on batteries or is plugged into a 1.2KW
capable wall outlet.

You should have read the opening synopsis. "Clock gating pushes the optimum
to deeper pipelines. Surprisingly, as leakage power grows, the optimum is
also found to shift to deeper pipelines."

The conclusions of the paper directly contradict your claims. In fact, if
you look at their calculations you'll see that for one of the workloads the
'performance only' optimum depth was 20 stages which, shazzam, is what the
original P4 pipeline was. In another workload type it came out at 22
stages. (note that it varies depending on what type of workload one
'assumes' and what one designs for) But then, as they explicitly say, "Even
though we model the complete processor pipeline, we only refer to the
stages between decode and execution as the pipeline length" so the numbers
are fewer than the total stages of a real processor. So the paper actually
supports the increased P4 pipelines rather than your contention. The longer
pipelines not only allow a faster clock but are 'raw performance optimal'.

It does not address at ALL what causes leakage, the thermal effects on
leakage, the effect of die power density, the process and how the
transistors are made, nor what the maximum achievable clock might be.
Which, unfortunately for you, happens to be where the problem lies.

Not to mention you ignore all the assumptions they explicitly list, and
there's a ton of them, with not the least being their definition for
'processor' excluding everything, like instruction cache, L2 cache, BUT the
(simplified) pipeline so naturally their 'processor power' is pipeline
power since it's the only thing they model (because pipeline length is the
only thing they're looking to 'optimize' as the title clearly says,
"Optimum Power/Performance Pipeline Depth," not "total processor power.").
Not to mention it's a minimal, simplified, model to demonstrate their
theory, not a complete processor, so your contention that their simplified
pipeline model 'power' represents the total power of a real processor made
on a real process is nonsensical.

And, of course, the primary reason power increases with the longer pipeline
is you CLOCK IT FASTER. It's a foregone conclusion in their analysis
because things like latch active (per clock) and leakage power (not to
mention they simply assume that power variation is due entirely to the
latches so power of the calculation logic itself is ignored) are static
plug-ins. As they say "This also explains why clock gating pushes the
optimum to greater pipeline depths. Clock gating reduces the power for a
given performance. Therefore, one can push the pipeline to larger
depths..." (because it reduces the effective clock rate on the latches by
not clocking each and every one on every clock cycle, assuming one CARES to
optimize work done per watt rather than raw performance.)

Even worse, for you, read on "However, a particularly interesting case
arises if we have complete clock gating on a fine grained scale. The
circuits and latches only switch with work changes; to first order,
pipelining itself does not lead to additional switching. However, it has
previously been shown that pipelining can lead to better performance. This
secondary effect can lead to changes in the switching behavior. The net
result is that the combined effects, of the increased frequency and reduced
clock gating switching with pipelining, become proportional to the
performance, (T/NI)-1. The effective switching frequency is proportional to
the number of instructions executed per unit time." In other words, in
theory, increased pipeline depth, alone, does not result in increased power
consumption; it's the MORE WORK per unit of time, I.E. better performance,
that a longer pipeline achieves that does.

So, regarding that tsunami, your paper says the added latches don't even
count for spit.

In short, you've done the same thing I previously warned you about: looking
for some 'little thing', a phrase, word, 'equation', you think 'looks like'
it'll support your foregone conclusion (whatever it happens to be at the
moment) without looking to see what's actually said or what it means and,
as a result, presented a paper that disproves everything you've contended.

"David Maynard" wrote in message
...

I don't need to email them because they know what they're talking about.
It's you who don't and misread it, not to mention misapply it to the
discussion. The paper does not say pipeline length causes leakage, as you erroneously
claimed,


It doesn't need to, it's obvious from the equation it uses. Research papers
assume their audience can understand basic equations.


You should have read the opening synopsis. "Clock gating pushes the optimum
to deeper pipelines. Surprisingly, as leakage power grows, the optimum is
also found to shift to deeper pipelines." The conclusions of the paper directly contradict
your claims. In fact, if you look at their calculations you'll see that for one of the
workloads the
'performance only' optimum depth was 20 stages which, shazzam, is what the
original P4 pipeline was.


Original Pentium 4??? We're comparing Prescotts here to Dothans.
Hello!!!



In another workload type it came out at 22
stages. (note that it varies depending on what type of workload one
'assumes' and what one designs for) But then, as they explicitly say, "Even
though we model the complete processor pipeline, we only refer to the
stages between decode and execution as the pipeline length" so the numbers
are fewer than the total stages of a real processor. So the paper actually
supports the increased P4 pipelines rather than your contention. The longer
pipelines not only allow a faster clock but are 'raw performance optimal'.

It does not address at ALL what causes leakage, the thermal effects on
leakage, the effect of die power density, the process and how the
transistors are made, nor what the maximum achievable clock might be.
Which, unfortunately for you, happens to be where the problem lies.


I never said that paper did that, just that it uses the equation that does.
Nevertheless, the paper does explicitly and conclusively say
that pipelines affect power. In Summary:

"A theory has been presented of the optimum pipeline
depth for a microprocessor taking into account both power
and performance. It was found that only one optimal
solution exists for this problem and the nature of that
solution has been characterized. For some
power/performance metrics one finds that the optimum
design contains only a single stage in the processor,
whereas for other metrics, including the performance only
metric, a pipelined design results. Consideration of power
in the optimization problem always leads to shorter
pipelines than if power were no consideration."




Not to mention you ignore all the assumptions they explicitly list, and
there's a ton of them, with not the least being their definition for
'processor' excluding everything, like instruction cache, L2 cache, BUT the
(simplified) pipeline so naturally their 'processor power' is pipeline
power since it's the only thing they model (because pipeline length is the
only thing they're looking to 'optimize' as the title clearly says,
"Optimum Power/Performance Pipeline Depth," not "total processor power.").
Not to mention it's a minimal, simplified, model to demonstrate their
theory, not a complete processor, so your contention that their simplified
pipeline model 'power' represents the total power of a real processor made
on a real process is nonsensical.


Assumptions in a modelling equation? You're joking! Of course there
are assumptions, all modelling equations make assumptions.


And, of course, the primary reason power increases with the longer pipeline
is you CLOCK IT FASTER. It's a foregone conclusion in their analysis
because things like latch active (per clock) and leakage power (not to
mention they simply assume that power variation is due entirely to the
latches so power of the calculation logic itself is ignored) are static
plug-ins. As they say "This also explains why clock gating pushes the
optimum to greater pipeline depths. Clock gating reduces the power for a
given performance. Therefore, one can push the pipeline to larger
depths..." (because it reduces the effective clock rate on the latches by
not clocking each and every one on every clock cycle, assuming one CARES to
optimize work done per watt rather than raw performance.)

Even worse, for you, read on "However, a particularly interesting case
arises if we have complete clock gating on a fine grained scale. The
circuits and latches only switch with work changes; to first order,
pipelining itself does not lead to additional switching. However, it has
previously been shown that pipelining can lead to better performance. This
secondary effect can lead to changes in the switching behavior. The net
result is that the combined effects, of the increased frequency and reduced
clock gating switching with pipelining, become proportional to the
performance, (T/NI)-1. The effective switching frequency is proportional to
the number of instructions executed per unit time." In other words, in
theory, increased pipeline depth, alone, does not result in increased power
consumption; it's the MORE WORK per unit of time, I.E. better performance,
that a longer pipeline achieves that does.


That's in the equation I cited, which you chose to ignore then
and say, "it's all about latches, eh?" The point was that latches and pipes
are quite important to power, as that equation shows and which the paper
also concludes, about which you're still hopelessly in denial.


So, regarding that tsunami, your paper says the added latches don't even
count for spit.


Yeah right! sigh

Raymond wrote:

"David Maynard" wrote in message
...

I don't need to email them because they know what they're talking about.
It's you who don't and misread it, not to mention misapply it to the
discussion. The paper does not say pipeline length causes leakage, as you erroneously
claimed,


It doesn't need to, it's obvious from the equation it uses.

Leakage is a plug-in to the equation: You pick what you 'think it is' and
go merrily on your way. There are no terms for heat generation, die power
density, or any other process characteristic.

Research papers
assume their audience can understand basic equations.

An unfortunate assumption on their part when it came to you reading it.

You should have read the opening synopsis. "Clock gating pushes the optimum
to deeper pipelines. Surprisingly, as leakage power grows, the optimum is
also found to shift to deeper pipelines." The conclusions of the paper directly contradict
your claims. In fact, if you look at their calculations you'll see that for one of the
workloads the
'performance only' optimum depth was 20 stages which, shazzam, is what the
original P4 pipeline was.


Original Pentium 4??? We're comparing Prescotts here to Dothans.
Hello!!!

No, 'we' weren't. The topic was deeper pipelines allowing faster clock
rates. You then went merrily dancing off into power dissipation as if it
'proved' something.

In another workload type it came out at 22
stages. (note that it varies depending on what type of workload one
'assumes' and what one designs for) But then, as they explicitly say, "Even
though we model the complete processor pipeline, we only refer to the
stages between decode and execution as the pipeline length" so the numbers
are fewer than the total stages of a real processor. So the paper actually
supports the increased P4 pipelines rather than your contention. The longer
pipelines not only allow a faster clock but are 'raw performance optimal'.

It does not address at ALL what causes leakage, the thermal effects on
leakage, the effect of die power density, the process and how the
transistors are made, nor what the maximum achievable clock might be.
Which, unfortunately for you, happens to be where the problem lies.


I never said that paper did that,

The discussion was whether increased heat generation was solely caused by
the mere existence of deeper pipelines (latches), what you think the
fallacious Dothan comparison shows, and you offered that paper as 'proof'.
It obviously doesn't 'prove' any such thing when it doesn't deal with any
of the process issues that determine leakage and power consumption, not to
mention it doesn't deal with the power of a 'whole processor' but merely
the portion they're concerned with optimizing. But the real kicker, for
you, is it's flat out declaration that deeper pipelines do not
automatically lead to increased power consumption, in direct contradiction
to your claim.

just that it uses the equation that does.

An equation you made claims about but clearly don't even begin to understand.

Nevertheless, the paper does explicitly and conclusively say
that pipelines affect power.

In Summary:

"A theory has been presented of the optimum pipeline
depth for a microprocessor taking into account both power
and performance. It was found that only one optimal
solution exists for this problem and the nature of that
solution has been characterized. For some
power/performance metrics one finds that the optimum
design contains only a single stage in the processor,
whereas for other metrics, including the performance only
metric, a pipelined design results. Consideration of power
in the optimization problem always leads to shorter
pipelines than if power were no consideration."


Of course pipelines 'affect power" because you use a deeper pipeline for
the express purpose of CLOCKING IT FASTER, for better performance, and
increased clock rates increase power consumption.

And if you give a tinker's dam about power, like in a battery powered
notebook, you might want to optimize for power. Otherwise you might want to
optimize for raw performance.


Not to mention you ignore all the assumptions they explicitly list, and
there's a ton of them, with not the least being their definition for
'processor' excluding everything, like instruction cache, L2 cache, BUT the
(simplified) pipeline so naturally their 'processor power' is pipeline
power since it's the only thing they model (because pipeline length is the
only thing they're looking to 'optimize' as the title clearly says,
"Optimum Power/Performance Pipeline Depth," not "total processor power.").
Not to mention it's a minimal, simplified, model to demonstrate their
theory, not a complete processor, so your contention that their simplified
pipeline model 'power' represents the total power of a real processor made
on a real process is nonsensical.


Assumptions in a modelling equation? You're joking! Of course there
are assumptions, all modelling equations make assumptions.

Quite right, there always are. And since you know that it's doubly
egregious of you to ignore every blessed one of them.


And, of course, the primary reason power increases with the longer pipeline
is you CLOCK IT FASTER. It's a foregone conclusion in their analysis
because things like latch active (per clock) and leakage power (not to
mention they simply assume that power variation is due entirely to the
latches so power of the calculation logic itself is ignored) are static
plug-ins. As they say "This also explains why clock gating pushes the
optimum to greater pipeline depths. Clock gating reduces the power for a
given performance. Therefore, one can push the pipeline to larger
depths..." (because it reduces the effective clock rate on the latches by
not clocking each and every one on every clock cycle, assuming one CARES to
optimize work done per watt rather than raw performance.)

Even worse, for you, read on "However, a particularly interesting case
arises if we have complete clock gating on a fine grained scale. The
circuits and latches only switch with work changes; to first order,
pipelining itself does not lead to additional switching. However, it has
previously been shown that pipelining can lead to better performance. This
secondary effect can lead to changes in the switching behavior. The net
result is that the combined effects, of the increased frequency and reduced
clock gating switching with pipelining, become proportional to the
performance, (T/NI)-1. The effective switching frequency is proportional to
the number of instructions executed per unit time." In other words, in
theory, increased pipeline depth, alone, does not result in increased power
consumption; it's the MORE WORK per unit of time, I.E. better performance,
that a longer pipeline achieves that does.


That's in the equation I cited,

If you see that the equation shows deeper pipelines, in and of themselves,
do not necessarily lead to increased power consumption then why did you
offer it as 'proof' that the mere existence of deeper pipelines must be the
sole cause of increased power consumption?

which you chose to ignore then
and say, "it's all about latches, eh?"

Because that's how you first presented it and was the 'point' you were
claiming to make, silly as it was.

The point was that latches and pipes
are quite important to power, as that equation shows

No, it doesn't. It shows that 'power in a pipeline' is "quite important" to
'power in a pipeline', at least within the scope of the bazillion
simplifying assumptions made, but it doesn't say a blessed thing about what
percentage of overall power consumption that is in a real 'whole' processor
made on a real process with real leakage and real thermal characteristics
nor does it address what the maximum achievable clock is or, indeed, any of
the ridiculous claims you've made, except for flat out declaring your
premise that the mere existence of more pipeline stages automatically means
more power dissipation to be false.

and which the paper
also concludes, about which you're still hopelessly in denial.

The only thing I deny are your nonsensical conclusions from not
understanding the very papers you reference.

So, regarding that tsunami, your paper says the added latches don't even
count for spit.


Yeah right! sigh

You now don't believe the paper you, yourself, presented?

David Maynard wrote:
Raymond wrote:
Original Pentium 4??? We're comparing Prescotts here to Dothans.
Hello!!!

No, 'we' weren't.

Thank you for that David, that was my reaction on first reading that. How he
can say that in a thread titled "Another Intel vs AMD Comparison" (Which I
believe he started himself) is beyond me. g

"Hello!!!" yourself Raymond.

Keep it up, I'm getting quite a few laughs out of watching this Raymond
character struggle to find articles to refute known facts, then misinterpret
them to suit himself (or simply becaue he's out of his depth). :-)
--
~Shaun~

"David Maynard" wrote in message
...
Raymond wrote:

"David Maynard" wrote in message
...

I don't need to email them because they know what they're talking about.
It's you who don't and misread it, not to mention misapply it to the
discussion. The paper does not say pipeline length causes leakage, as you erroneously
claimed,


It doesn't need to, it's obvious from the equation it uses.

Leakage is a plug-in to the equation: You pick what you 'think it is' and
go merrily on your way. There are no terms for heat generation, die power
density, or any other process characteristic.

Not it isn't. read it. The plug-in is leakage factor not total leakage,
ie a leakage/latch factor. More pipeline stages = more latches =
more total leakage power!

Research papers
assume their audience can understand basic equations.

An unfortunate assumption on their part when it came to you reading it.

The unfortunate assumption applies to you here, obviously.


Assumptions in a modelling equation? You're joking! Of course there
are assumptions, all modelling equations make assumptions.

Quite right, there always are. And since you know that it's doubly
egregious of you to ignore every blessed one of them.

Well we have a choice, despite the assumptions:

1) an equation that explains most of the discrepancy in power
consumption to the comparison I described.

2) your theory: there are too many factors, I give up.


Hmmm, tough one. I think I'm going to have to go with #1 here.
Sorry!

Raymond wrote:

"David Maynard" wrote in message
...

Raymond wrote:


"David Maynard" wrote in message
...

I don't need to email them because they know what they're talking about.
It's you who don't and misread it, not to mention misapply it to the
discussion. The paper does not say pipeline length causes leakage, as you erroneously
claimed,


It doesn't need to, it's obvious from the equation it uses.

Leakage is a plug-in to the equation: You pick what you 'think it is' and
go merrily on your way. There are no terms for heat generation, die power
density, or any other process characteristic.


Not it isn't.

Yes, it is.

read it. The plug-in is leakage factor not total leakage,

So who said it was total leakage? Not I.

ie a leakage/latch factor.

Yes, that's the number you plug-in. You pick a number and plug it into the
equation. That's why it's called a plug-in.

More pipeline stages = more latches =
more total leakage power!

Why don't you ever read what's written? To repeat what's already up there
"There are no terms for heat generation, die power density, or any other
process characteristic" which dynamically alter leakage, in the real world.

It's a blooming static plug-in. And the latches do not 'cause' leakage; you
plug in the number, whatever caused it. Except, unfortunately for the
equation, it isn't static.

As the paper says in Section 5, "The leakage power was
varied between 0% and 90% of the total power dissipation."

Pick a number. Plug it in. Have fun. And never mind that, in the real
world, it changes with temperature.

Not to mention you have idea what to plug in for *any* of the numbers or
what portion of the total power in a real processor the equation even deals
with.

Research papers
assume their audience can understand basic equations.

An unfortunate assumption on their part when it came to you reading it.


The unfortunate assumption applies to you here, obviously.

LOL

I mean, really, that *is* funny coming from you who's main approach in this
discussion is to snip out and ignore every single technical issue.


Assumptions in a modelling equation? You're joking! Of course there
are assumptions, all modelling equations make assumptions.

Quite right, there always are. And since you know that it's doubly
egregious of you to ignore every blessed one of them.


Well we have a choice, despite the assumptions:

1) an equation that explains most of the discrepancy in power
consumption to the comparison I described.

That would be great if it weren't for the fact that the equation does no
such thing because, just to reiterate a few, the numbers are static
plug-ins, it doesn't concern itself with the total power of a complete
processor, and it speaks not at all to process issues.


2) your theory: there are too many factors, I give up.

Except I never said "too many factors" nor "I give up." I said you ignore
all the other factors and had explained to you back at the very beginning
of this farce that the main problem was the process and temperature
dependent leakage current aggravated by power consumption forming, to some
degree, a regenerative leakage-power-temperature-leakage--- feedback loop
that beings because you CLOCK IT FASTER.


Hmmm, tough one. I think I'm going to have to go with #1 here.
Sorry!

Well, let's not insult the good folk who wrote that paper by suggesting
their excellent research had anything to do with it, especially since their
paper contradicts everything you've contended, because it's abundantly
clear that nothing written by either man or god could alter your
preconceived fallacies.