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#51
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"James Hanley" wrote in message...
Course Neither Dual inline nor DDR increase the actual speed. You have to be careful with your terminology here, as you're in danger of confusing/transposing different factors. In particular it looks like you're a little too keen to mix bus speeds and bandwidths. However, DDR is considered to increase the effective speed, even though it does not increase the speed in cycles per second. Double data rate increases bandwidth, not speed. ;-) It just writes twice as much per cycle, which has the same effect as working at twice the frequency. Correct. according to the table in pcguide.com article "Memory Banks and Package Bit Width", it says Pentiums have a 64-bit data bus. Yes, eight bytes/64 bits. I mentioned this in my previous post. So a Pentium with DDR RAM DIMMS has a 64-bit data bus and 64-bit memory bus. If the effective speeds are the same, - for example - the actual FSB is the same, the FSB is dual pumped and so is the memory bus, No. The front side bus on the Pentium 4 CPU's is *quad* pumped, so four data transfers per clock, not two as you say above. If the memory bus can throw around twice as much data as the FSB, then it is not an efficient set up. That comment is incorrect, because your underlying assumption about the P4 processor bus being double pumped is wrong. It is only efficient if the DDR RAM is half the speed of the FSB. See above. Since in one memory bus clock cycle when reading, there are 2 servings for the FSB, it would require 2 FSB cycles to pick up the data. Similarly when writing. No. See above. No, that's wrong. You're ass-u-ming that the geometry of the processor and memory buses are the same. In most cases they're not. yeah, I was assuming that, but based on the tables I saw at pcguide.com and scott mueller's article. Collectively they said that Pentiums have 64-bit data buses and DDR RAM (at least PC66- PC4300) has 64-bit memory bus. They do. To me, that means that the geometry is the same. No. You're forgetting that one is DDR and the other QDR. Snip RH's explanation of P4 and DDR bus geometry but isn't that a beautiful real world illustration of what I mean. Lol, depends what you're talking about, as you've just spent the first half of this post claiming that the memory bus runs twice as quick as the processor bus, so do you mind telling us exactly what you do mean? In that example, the effective speed of the FSB is 800=4*200. And the effective speed of the memory bus is 400=2*200. It's efficient, because the bandwidth is equal. Correct. Although that required the actual speeds to be the same, it means that the FSB's effective speed is half that of the memory bus. Eh? You seem to be confusing yourself with all this talk of "effective speeds". The Pentium 4 bus's "effective speed" (as you call it) is four times faster than the FSB clock, as there are four transfers per clock (QDR), so the FSB's effective speed is twice that of the DDR memory bus, but, to compensate, a dual channel DDR memory bus is twice as wide as the processor's. When you say "If you keep your memory synchronous, you also raise the bandwidth of the memory bus by 33%." You mean keeping the actual memory speed equal to the processor speed, right? Yes. The word synchronous is a funny one to use, because SDRAM is always synchronous, that's what the S stands for. The "S" in SDRAM is there partly for marketing reasons, partly because it refers to the way the memory works inside each DIMM. You need to separate the term "Synchronous" (capital S) as it applies to SDRAM memory modules from the word "synchronous". If the actual speeds are different, it would stiull be synchronous, No. You have to understand that "synchronous" (small s) is just a verb that could be used in any scenario. Could even say that my girlfriend's heart is synchronous to mine when they start beating together, but that's another story. ;-) It literally refers to things running at the same speed. In this scenario, when I say that the FSB and memory buses are synchronous, it means they're running at a 1:1 multiplier. No more or less. If I say the memory and processor buses are asynchronous, it means that the multiplier is something other than 1:1. If, OTOH, you keep the FSB the same, but raise the CPU and memory multipliers by 33%, you get the faster memory and CPU clocks, but you don't raise the processor bus, so the resulting bottleneck - assuming that the bandwidths matched in the first place - will curtail your performance gain. And in your earlier example P4 800MHz FSB(200*4). DDR-SDRAM PC3200 400MHz=(200*2) - a 2:1 multiplier. There's no bottleneck because the bandwidths of the fsb and memory bus are equal. Yep, sure, assuming that the memory was dual channel, the bandwidths would match. What I was trying to say though, was that, if you assumed that the CPU in the system above was an engineering sample, your "FSB doesn't matter" theory would be comprehensively disproved by the following test: Test configuration A: CPU multiplier: 12x FSB: 266MHz FSB:Memory bus multiplier: 1:1 Test configuration B: CPU multiplier: 18x FSB: 200MHz FSB:Memory bus multiplier: 3:4 In the configurations above, CPU core speed A=CPU core speed B, while memory bus speed A=memory bus speed B, give or take any floating point differences. However, in configuration A, the processor bus bandwidth would be 8.5GB/sec, theoretically matched to the memory bandwidth. In configuration B, the processor bus bandwidth would be reduced to 6.4GB/sec, creating the bottleneck. Even allowing for inefficiency and latency in the memory bus, configuration A should still have a tidy performance advantage, despite, processor and memory speeds being the same. yeah, and those calculations i did with the 33% increase all agree with what you're saying. thanks No worries. :-) -- Richard Hopkins Cardiff, Wales, United Kingdom (replace .nospam with .com in reply address) The UK's leading technology reseller www.dabs.com Get the most out of your digital photos www.dabsxpose.com |
#52
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"James Hanley" wrote in message...
Course Neither Dual inline nor DDR increase the actual speed. You have to be careful with your terminology here, as you're in danger of confusing/transposing different factors. In particular it looks like you're a little too keen to mix bus speeds and bandwidths. However, DDR is considered to increase the effective speed, even though it does not increase the speed in cycles per second. Double data rate increases bandwidth, not speed. ;-) It just writes twice as much per cycle, which has the same effect as working at twice the frequency. Correct. according to the table in pcguide.com article "Memory Banks and Package Bit Width", it says Pentiums have a 64-bit data bus. Yes, eight bytes/64 bits. I mentioned this in my previous post. So a Pentium with DDR RAM DIMMS has a 64-bit data bus and 64-bit memory bus. If the effective speeds are the same, - for example - the actual FSB is the same, the FSB is dual pumped and so is the memory bus, No. The front side bus on the Pentium 4 CPU's is *quad* pumped, so four data transfers per clock, not two as you say above. If the memory bus can throw around twice as much data as the FSB, then it is not an efficient set up. That comment is incorrect, because your underlying assumption about the P4 processor bus being double pumped is wrong. It is only efficient if the DDR RAM is half the speed of the FSB. See above. Since in one memory bus clock cycle when reading, there are 2 servings for the FSB, it would require 2 FSB cycles to pick up the data. Similarly when writing. No. See above. No, that's wrong. You're ass-u-ming that the geometry of the processor and memory buses are the same. In most cases they're not. yeah, I was assuming that, but based on the tables I saw at pcguide.com and scott mueller's article. Collectively they said that Pentiums have 64-bit data buses and DDR RAM (at least PC66- PC4300) has 64-bit memory bus. They do. To me, that means that the geometry is the same. No. You're forgetting that one is DDR and the other QDR. Snip RH's explanation of P4 and DDR bus geometry but isn't that a beautiful real world illustration of what I mean. Lol, depends what you're talking about, as you've just spent the first half of this post claiming that the memory bus runs twice as quick as the processor bus, so do you mind telling us exactly what you do mean? In that example, the effective speed of the FSB is 800=4*200. And the effective speed of the memory bus is 400=2*200. It's efficient, because the bandwidth is equal. Correct. Although that required the actual speeds to be the same, it means that the FSB's effective speed is half that of the memory bus. Eh? You seem to be confusing yourself with all this talk of "effective speeds". The Pentium 4 bus's "effective speed" (as you call it) is four times faster than the FSB clock, as there are four transfers per clock (QDR), so the FSB's effective speed is twice that of the DDR memory bus, but, to compensate, a dual channel DDR memory bus is twice as wide as the processor's. When you say "If you keep your memory synchronous, you also raise the bandwidth of the memory bus by 33%." You mean keeping the actual memory speed equal to the processor speed, right? Yes. The word synchronous is a funny one to use, because SDRAM is always synchronous, that's what the S stands for. The "S" in SDRAM is there partly for marketing reasons, partly because it refers to the way the memory works inside each DIMM. You need to separate the term "Synchronous" (capital S) as it applies to SDRAM memory modules from the word "synchronous". If the actual speeds are different, it would stiull be synchronous, No. You have to understand that "synchronous" (small s) is just a verb that could be used in any scenario. Could even say that my girlfriend's heart is synchronous with mine when they start beating together, but I'd never use such a clinical word to describe such a lovely thing. ;-) Synchronous literally refers to things running at the same speed. In this scenario, when I say that the FSB and memory buses are synchronous, it means they're running at a 1:1 multiplier. No more or less. If I say the memory and processor buses are asynchronous, it means that the multiplier is something other than 1:1. If, OTOH, you keep the FSB the same, but raise the CPU and memory multipliers by 33%, you get the faster memory and CPU clocks, but you don't raise the processor bus, so the resulting bottleneck - assuming that the bandwidths matched in the first place - will curtail your performance gain. And in your earlier example P4 800MHz FSB(200*4). DDR-SDRAM PC3200 400MHz=(200*2) - a 2:1 multiplier. There's no bottleneck because the bandwidths of the fsb and memory bus are equal. Yep, sure, assuming that the memory was dual channel, the bandwidths would match. What I was trying to say though, was that, if you assumed that the CPU in the system above was an engineering sample, your "FSB doesn't matter" theory would be comprehensively disproved by the following test: Test configuration A: CPU multiplier: 12x FSB: 266MHz FSB:Memory bus multiplier: 1:1 Test configuration B: CPU multiplier: 18x FSB: 200MHz FSB:Memory bus multiplier: 3:4 In the configurations above, CPU core speed A=CPU core speed B, while memory bus speed A=memory bus speed B, give or take any floating point differences. However, in configuration A, the processor bus bandwidth would be 8.5GB/sec, theoretically matched to the memory bandwidth. In configuration B, the processor bus bandwidth would be reduced to 6.4GB/sec, creating the bottleneck. Even allowing for inefficiency and latency in the memory bus, configuration A should still have a tidy performance advantage, despite, processor and memory speeds being the same. yeah, and those calculations i did with the 33% increase all agree with what you're saying. thanks No worries. :-) -- Richard Hopkins Cardiff, Wales, United Kingdom (replace .nospam with .com in reply address) The UK's leading technology reseller www.dabs.com Get the most out of your digital photos www.dabsxpose.com |
#53
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"Richard Hopkins" wrote in message ...
"James Hanley" wrote in message... Course Neither Dual inline nor DDR increase the actual speed. You have to be careful with your terminology here, as you're in danger of confusing/transposing different factors. In particular it looks like you're a little too keen to mix bus speeds and bandwidths. I slipped up before with the dual punped, quad pomped thing What I meant was that with the p4 running dual inline memory modules, is efficient, no bottleneck. Also, the P4's effective speed of 800(200*4) compared to the memory's effective speed of 400(200*2). is double. To compensate, the memory serves double, since its width is doubled, and the system is efficient. However, DDR is considered to increase the effective speed, even though it does not increase the speed in cycles per second. Double data rate increases bandwidth, not speed. ;-) but since the concept of 'effective speed' was invented, memory that is DDR with an actual clock of 200MHz, is said to have an effective speed of 400MHz, it's called DDR 400. Even though it does not increase speed or cycles per second, it just increases bandwidth. Dual inline also only increases bandwidth, but oddly, it's considered not to increase 'effective speed'. Perhaps the term/concept of 'effective speed' should not be used when discussing what's actually happening. It's just useful to some for calculating bandwidth, so the FSB's bandwidth of 800*8 comes up the same as 200*(4*8). |
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