AMD has the answer for Intel

On Mon, 13 Oct 2003 21:53:24 -0400, Keith R. Williams wrote:

In article ,
says...
On Mon, 13 Oct 2003 07:12:54 -0400, George Macdonald wrote:

Neither Keith nor I is arguing with you on the MHz for "data rates"...
though you seem to be trying hard to keep *some* quarrel alive. When you
argue with the folks who are agreeing with you, it's umm, kinda hard to
fathom.:-P

OTOH you still have not acknowledged that the base common clock is *not*
the only clock at play here. There *are* indeed four separate pairs of
strobe clocks for the source synchronous data transfers and they run at
double the frequency of the common clock, i.e. for the 200MHz FSB, 800MT/s
data rate, 400MHz.

I haven't acknowledged it because I haven't looked at it because the base
clock is the only clock that really matters when it comes to defining the
FSB clock speed IMO, and I guess yours too. I really don't care how the
data is pulled off the base clock when it gets to the cpu as this is
something that there is no control over by the user or even a MB
manufacturer. It's not adjustable but a basic design of the cpu and will
always be constant based on the base clock (FSB speed).

Gee Wes, I suppose you'd support an argument that all PCs since
the IBM 5150 run at 14.31818 MHz?

Don't know, or care what the IBM 5150 is, and I'm sure not going to waste
my time getting the data on it.

Get a clue (or take any of the free one's offered here), you
haven't a leg to stand on.

On what issue? There's only one issue I've ever made a statement about
here and that's using bogus MHz numbers for the FSB. you've already agreed
with me on that so I don't even know what you are talking about.

I couldn't care less about the actual timings of the data ticks since it
isn't adjustable. Ther's 4 ticks per clock no matter what the clock is.

--
Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB)
http://mysite.verizon.net/res0exft/cpu.html

In article ,
says...
On Mon, 13 Oct 2003 21:53:24 -0400, Keith R. Williams wrote:

In article ,
says...
On Mon, 13 Oct 2003 07:12:54 -0400, George Macdonald wrote:

Neither Keith nor I is arguing with you on the MHz for "data rates"...
though you seem to be trying hard to keep *some* quarrel alive. When you
argue with the folks who are agreeing with you, it's umm, kinda hard to
fathom.:-P

OTOH you still have not acknowledged that the base common clock is *not*
the only clock at play here. There *are* indeed four separate pairs of
strobe clocks for the source synchronous data transfers and they run at
double the frequency of the common clock, i.e. for the 200MHz FSB, 800MT/s
data rate, 400MHz.

I haven't acknowledged it because I haven't looked at it because the base
clock is the only clock that really matters when it comes to defining the
FSB clock speed IMO, and I guess yours too. I really don't care how the
data is pulled off the base clock when it gets to the cpu as this is
something that there is no control over by the user or even a MB
manufacturer. It's not adjustable but a basic design of the cpu and will
always be constant based on the base clock (FSB speed).

Gee Wes, I suppose you'd support an argument that all PCs since
the IBM 5150 run at 14.31818 MHz?

Don't know, or care what the IBM 5150 is, and I'm sure not going to waste
my time getting the data on it.

Umm, the *original* IBM PC, from 1981. Sheesh, I thought you
were the PC 'spurt!

Get a clue (or take any of the free one's offered here), you
haven't a leg to stand on.

On what issue? There's only one issue I've ever made a statement about
here and that's using bogus MHz numbers for the FSB. you've already agreed
with me on that so I don't even know what you are talking about.

You're 1/4 number. As has been 'splained to you many times, the
interface uses 1/2 clocking, via the slice strobes. That makes
it, under any definition a 400MHz bus. Indeed the fastest thing
happening (including data lines) is at 400MHz (maybe).

I couldn't care less about the actual timings of the data ticks since it
isn't adjustable.

You haven't a clue. It's not the common clock, it's the
frequency of the bus. The common clock may generate the strobes,
but the 14.31818 MHz system oscillator generates *all* the
processor clocks/strobes. Your argument doesn't hold water.

Ther's 4 ticks per clock no matter what the clock is.

Nope. The slice strobes run the channel.

--
Keith

On Tue, 14 Oct 2003 20:58:11 -0400, Keith R. Williams wrote:

In article ,
says...
On Mon, 13 Oct 2003 21:53:24 -0400, Keith R. Williams wrote:

In article ,
says...
On Mon, 13 Oct 2003 07:12:54 -0400, George Macdonald wrote:

Gee Wes, I suppose you'd support an argument that all PCs since
the IBM 5150 run at 14.31818 MHz?

Don't know, or care what the IBM 5150 is, and I'm sure not going to waste
my time getting the data on it.

Umm, the *original* IBM PC, from 1981. Sheesh, I thought you
were the PC 'spurt!

Saw it. Considered it trash and didn't buy one. Bought a 286 a little
later to port a program I had written over to the x86 at the request of
several PC types. And I've never bought a complete system. I'always put my
own together, so manufacturer model numbers don't mean Jack to me.

Get a clue (or take any of the free one's offered here), you
haven't a leg to stand on.

On what issue? There's only one issue I've ever made a statement about
here and that's using bogus MHz numbers for the FSB. you've already agreed
with me on that so I don't even know what you are talking about.

You're 1/4 number. As has been 'splained to you many times, the
interface uses 1/2 clocking, via the slice strobes. That makes
it, under any definition a 400MHz bus. Indeed the fastest thing
happening (including data lines) is at 400MHz (maybe).

Sorry. I just don't buy using that as a valid FSB speed designation. The
base clock is the only valid one I will ever consider. Anything else with
MHz behind it in reference to the FSB is just pure BS. If you want to talk
data bits, use the proper terminology for data rates. You can throw all
kinds of bull**** at this you want to. it still won't make it right.

I couldn't care less about the actual timings of the data ticks since it
isn't adjustable.

You haven't a clue. It's not the common clock, it's the
frequency of the bus. The common clock may generate the strobes,
but the 14.31818 MHz system oscillator generates *all* the
processor clocks/strobes. Your argument doesn't hold water.

Christ, you are grasping at straws now. WTF does this have to do with the
FSB, other than that may be the base clock of the clock generator which
genrates the bus clock.

Ther's 4 ticks per clock no matter what the clock is.

Nope. The slice strobes run the channel.

I thought you would understand that I meant the bus was QDR.

--
Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB)
http://mysite.verizon.net/res0exft/cpu.html

On Wed, 15 Oct 2003 04:49:35 GMT, "Wes Newell"
wrote:



You haven't a clue. It's not the common clock, it's the
frequency of the bus. The common clock may generate the strobes,
but the 14.31818 MHz system oscillator generates *all* the
processor clocks/strobes. Your argument doesn't hold water.

Christ, you are grasping at straws now. WTF does this have to do with the
FSB, other than that may be the base clock of the clock generator which
genrates the bus clock.

Uh-huh - there shall be only one clock and no other clocks.shrug

Ther's 4 ticks per clock no matter what the clock is.

Nope. The slice strobes run the channel.

I thought you would understand that I meant the bus was QDR.

And pray tell what does QDR mean????

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??

On Wed, 15 Oct 2003 08:28:14 -0400, George Macdonald wrote:

On Wed, 15 Oct 2003 04:49:35 GMT, "Wes Newell"
wrote:

I thought you would understand that I meant the bus was QDR.

And pray tell what does QDR mean????

My own offshoot of DDR, Quad Data Rate. Easier than typing quad pumped.

--
Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB)
http://mysite.verizon.net/res0exft/cpu.html

On Wed, 15 Oct 2003 21:20:25 GMT, "Wes Newell"
wrote:

On Wed, 15 Oct 2003 08:28:14 -0400, George Macdonald wrote:

On Wed, 15 Oct 2003 04:49:35 GMT, "Wes Newell"
wrote:

I thought you would understand that I meant the bus was QDR.

And pray tell what does QDR mean????

My own offshoot of DDR, Quad Data Rate. Easier than typing quad pumped.

I know what the letters mean. The thing is do you? IOW how does one
achieve QDR signalling... apparently with the bus' base clock?

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??

On Thu, 16 Oct 2003 08:19:47 -0400, George Macdonald wrote:

On Wed, 15 Oct 2003 21:20:25 GMT, "Wes Newell"
wrote:

On Wed, 15 Oct 2003 08:28:14 -0400, George Macdonald wrote:

On Wed, 15 Oct 2003 04:49:35 GMT, "Wes Newell"
wrote:

I thought you would understand that I meant the bus was QDR.

And pray tell what does QDR mean????

My own offshoot of DDR, Quad Data Rate. Easier than typing quad pumped.

I know what the letters mean. The thing is do you? IOW how does one
achieve QDR signalling... apparently with the bus' base clock?

No. I don't know the exact way Intel does it. Nor do I care. I haven't
owned an Intel proc. since I last used a 486SX20. And this is the AMD
overclocking ng. I don't know who started the cross posting. So save your
typing fingers, I'm not interested.

--
Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB)
http://mysite.verizon.net/res0exft/cpu.html

No. I don't know the exact way Intel does it. Nor do I care. I haven't
owned an Intel proc. since I last used a 486SX20. And this is the AMD
overclocking ng. I don't know who started the cross posting. So save your
typing fingers, I'm not interested.

comp.sys.IBM.PC.chips, I don't know if you're posting this from
alt.comp.hardware.overclocking.amd, but this thread definitely is more
appropriate to the former.

In article ,
says...
On Thu, 16 Oct 2003 08:19:47 -0400, George Macdonald wrote:

On Wed, 15 Oct 2003 21:20:25 GMT, "Wes Newell"
wrote:

On Wed, 15 Oct 2003 08:28:14 -0400, George Macdonald wrote:

On Wed, 15 Oct 2003 04:49:35 GMT, "Wes Newell"
wrote:

I thought you would understand that I meant the bus was QDR.

And pray tell what does QDR mean????

My own offshoot of DDR, Quad Data Rate. Easier than typing quad pumped.

I know what the letters mean. The thing is do you? IOW how does one
achieve QDR signalling... apparently with the bus' base clock?

No. I don't know the exact way Intel does it. Nor do I care.

SO we all agree. You haven't a clue what you're talking about.
The only difference I see here is that George and I have some
interest in technical correctness.

I haven't
owned an Intel proc. since I last used a 486SX20. And this is the AMD
overclocking ng.

Wrong! Look again. At issue has been the Intel FSB, not what
you think it "should be". You're the one who has butted into a
discussion, sans information.

I don't know who started the cross posting. So save your
typing fingers, I'm not interested.

It's been cross-posted to where I (and I assume George, since
he's regular on .chips too) have been since the beginning. You
really do need to rent a clue. Try arguing with your fellow
over-clockers, rather than those who are trying to give you a
clue.

--
Keith

In article ,
says...
No. I don't know the exact way Intel does it. Nor do I care. I haven't
owned an Intel proc. since I last used a 486SX20. And this is the AMD
overclocking ng. I don't know who started the cross posting. So save your
typing fingers, I'm not interested.

comp.sys.IBM.PC.chips, I don't know if you're posting this from
alt.comp.hardware.overclocking.amd, but this thread definitely is more
appropriate to the former.

Why? We were discussing the P4 bus. Is that something the AMD
over-clockers (sad lot that is) are all that interested in?

--
Keith