Intel working on Z-RAM too

In article . com,
says...

Del Cecchi wrote:
David Kanter wrote:
Yousuf Khan wrote:

David Kanter wrote:

You heard Del say no such thing. I said there was a heated debate,
which is a long way from "huge fight". Back in the day there was honest
disagreement over the magnitude of the power and performance difference.

My apologies if I mischaracterized your statement. The point remains:
certain elements within IBM clearly did not believe that SOI was worth
it, and wanted to stick with bulk.

You still can't get it right! You certainly are blind.

And SOI is not just being used for "high end stuff". It just isn't
being used for Standard Cell ASIC chips.

Perhaps our definition of high end vary...

Moving the goal-posts again. Why am I not surprised.

SOI adds substantial costs, it would also force Intel to totally rework
their circuit stuff, etc. etc. And frankly, SOI is worth less and less
performance at every node.

Gee, I haven't heard that. Who told you that? Have you done
measurements? Run 3D field simulations? Or was this Intel spin?
Remember sometimes spin is true and sometimes it isn't.

This was information from an engineer in Canada who used to post to
comp.arch. I have no particular reason to disbelieve what he said,
although I'm certainly open to listening to other POVs. I believe I've
already indicated that I'm not an EE, physicist nor do I run sims. I
would point out that there is some information on the relative merits
of the different processes:

You admit that you're nothing but an Intel gad-fly? At least
you're being honest today.

http://www.realworldtech.com/page.cf...005001504&p=14

This article, written by David Wang, shows a cross comparison of
different process technologies. In looking at the 65nm nodes, we can
compare the IBM process to the joint IBM/AMD/Toshiba/Sony. It appears
that the Ion for ITSA is slightly higher, while Intel's Ioff is about
2x lower. Of course, Intel's high Vt transistors have substantially
less leakage (factor of ~10) than the low Vt, at the cost of worse Ion
performance.

Do you know what this means? I didn't think so.

If I made any errors in reading the chart, I'd be more than happy to
accept corrections.

Also, for those who were curious about SRAM cell sizes, they are
included in the chart.

Different strokes for different folks.

Myself, I really don't know the numbers for SOI advantage at 65 or 45nm
process nodes.

The chart above does have some information, and the rest of the article
has more. One caveat is that I'm not sure whether these numbers
include the later modifications to the process.

Of course you don't know. You have no degree in anything relevant,
remember?

Sure, I can buy a cell phone for 20 dollars at walmart and it provides a
useful service to the average person, even in a LDC. What use is a PC
to the average person in a LDC?

It's a rather useful educational tool. Word processing, spread sheets,
email, wikipedia, developing. All sorts of things you can do.

It's a *USELESS* educational tool, for anything other than learning
how to use a computer. PC's aren't likely to teach a third-world
farmer how to increase his crop yield. He has more important
things to learn than WinBlows.

--
Keith

In article om,
says...
Northstar had one form of multithreading, the one that could be added
economically. It was enough of a win that it was carried forward for
several generations of processors.

Absolutely. I'm not denigrating SoEMT; I'm just pointing out that it's
not SMT, and Keith should know better than to try to foist that fallacy
on us.

You're a piece of work. What about the /195 and /95 (known as dual
I-stream then)?

Interesting, I hadn't heard of either.

You've ignored every previous comment I've made about these,
dismissing them as "PowerPC" products boggle. Clearly you have
no clue and refuse to buy one.

I tried searching and I found
this:
http://www-03.ibm.com/ibm/history/ex...me_PP2195.html

Could you provide a link that might have more technical details? I'd
be interested in learning about the 195.

This stuff wasn't much ballyhooed in the '60s. No one would have
understood it. Perhaps you want to ask more on an appropriate
forum?

Keith, you are making a rather extraordinarily claim. SMT became a
well defined term in the mid 1990's due to the work of the SMT group at
UW. I have read several of their research and I haven't found a single
reference to such a beast. Certainly, academics have a responsibility
when submitting refereed papers to cite and discuss prior work.

New terms are what academia is all about. Have you researched the
/195? I suggest that you do. "New" things tend not to be so new,
just the costs come down.

If you look at "simultaneous multithreading: maximizing on-chip
parallelism", the seminal paper, particularly section 7, I see no
mention of such a processor from IBM (although I did not read all the
papers referenced, merely looked for titles indicating IBM or the 195).
Given the folks that the SMT group collaborated (including Joel Emer
of DEC), I have a hard time believing that they simply 'forgot' the
existence of a prior processor which implemented all the key features
of SMT. There were some processors that implemented SMT, but they were
special purpose (ray tracing), lacking caches, etc. etc.

Why not look at the "micro"-architecture of the /195? The Dual I-
Stream isn't so much different. Two instructions streams from the
I-box being fed into the E-box so it had something to do if either
'I's took a branch.

All together, it seems to me that the burden of proof rests upon your
shoulders to show:
1. What the 195 is.

WOW If you have to ask this, clearly you're not capable of
holding up your end of any such argument. ...not to mention the
/95.

2. That it actually implemented SMT

Do some more research. SMT, as you narrowly define it? Maybe not.
here is little new under the sun though. Perhaps you'd like to
follow Intel's SMT patents backwards?

You have done neither, and rather indicated that "I need to ask
elsewhere". It seems to me that if you wish to debunk what seems to be
reasonably well accepted truth, you should be willing to back up, with
references...rather than simply claim the existence of a counter
example without substantiation.

No, I'm calling out your typical technology "expertise" crap and
telling you to look further. You can't, not that you'd understand
it anyway.

--
Keith

krw wrote:
In article . com,
says...

Del Cecchi wrote:
David Kanter wrote:
Yousuf Khan wrote:

David Kanter wrote:

My apologies if I mischaracterized your statement. The point remains:
certain elements within IBM clearly did not believe that SOI was worth
it, and wanted to stick with bulk.

You still can't get it right! You certainly are blind.

According to Del "As Keith knows, there was a heated debate within IBM
over the merits of
SOI. And today the IBM Fab manufactures both bulk and SOI."

That there was a debate clearly means that some folks had differing
views on the merits of SOI. Now at the conclusion of the debate, the
doubters were either overruled or convinced of the merits of SOI.
However, just because the outcome went one way at IBM does not
guarantee that the outcome will go the same at Intel.

There are plenty of companies that design MPUs, DSPs, etc. etc. and
their processes vary quite a bit. Some have more metal layers, some
have less, some use SOI, some don't. If you think I'm so blind perhaps
you could enlighten us all with your knowledge and explain what I'm
missing?

[snip]

http://www.realworldtech.com/page.cf...005001504&p=14

This article, written by David Wang, shows a cross comparison of
different process technologies. In looking at the 65nm nodes, we can
compare the IBM process to the joint IBM/AMD/Toshiba/Sony. It appears
that the Ion for ITSA is slightly higher, while Intel's Ioff is about
2x lower. Of course, Intel's high Vt transistors have substantially
less leakage (factor of ~10) than the low Vt, at the cost of worse Ion
performance.

Do you know what this means? I didn't think so.

Keith, most of the terms are defined (perhaps informally, but defined
nonetheless) earlier in the article.

If I made any errors in reading the chart, I'd be more than happy to
accept corrections.

Also, for those who were curious about SRAM cell sizes, they are
included in the chart.

Different strokes for different folks.

This point went back to earlier in the thread when discussing SRAM
density.

Myself, I really don't know the numbers for SOI advantage at 65 or 45nm
process nodes.

The chart above does have some information, and the rest of the article
has more. One caveat is that I'm not sure whether these numbers
include the later modifications to the process.

Of course you don't know. You have no degree in anything relevant,
remember?

You know, some of the best computer architects I've spoken with don't
have relevant degrees. Take John McCalpin; he got a PhD in Physical
Oceanography. Now that sounds irrelevant to computer architecture, but
last time I heard he did some good things at SGI, at IBM and now at
AMD. Besides, I rather doubt you know enough about my academic
background to make judgments.

DK

krw wrote:
In article om,
says...
Northstar had one form of multithreading, the one that could be added
economically. It was enough of a win that it was carried forward for
several generations of processors.

Absolutely. I'm not denigrating SoEMT; I'm just pointing out that it's
not SMT, and Keith should know better than to try to foist that fallacy
on us.

You're a piece of work. What about the /195 and /95 (known as dual
I-stream then)?

Interesting, I hadn't heard of either.

You've ignored every previous comment I've made about these,
dismissing them as "PowerPC" products boggle. Clearly you have
no clue and refuse to buy one.

I tried searching and I found
this:
http://www-03.ibm.com/ibm/history/ex...me_PP2195.html

Could you provide a link that might have more technical details? I'd
be interested in learning about the 195.

This stuff wasn't much ballyhooed in the '60s. No one would have
understood it. Perhaps you want to ask more on an appropriate
forum?

Keith, you are making a rather extraordinarily claim. SMT became a
well defined term in the mid 1990's due to the work of the SMT group at
UW. I have read several of their research and I haven't found a single
reference to such a beast. Certainly, academics have a responsibility
when submitting refereed papers to cite and discuss prior work.

New terms are what academia is all about. Have you researched the
/195? I suggest that you do. "New" things tend not to be so new,
just the costs come down.

I tried looking into the /195, but there's not much online about it.
The only reference I can find is a paper: JO Murphey, RM Wade -
Datamation, 1970

Which is not available online. Given the date, it's clearly a dead
tree journal, and probably one that hasn't been OCRed.

If you look at "simultaneous multithreading: maximizing on-chip
parallelism", the seminal paper, particularly section 7, I see no
mention of such a processor from IBM (although I did not read all the
papers referenced, merely looked for titles indicating IBM or the 195).
Given the folks that the SMT group collaborated (including Joel Emer
of DEC), I have a hard time believing that they simply 'forgot' the
existence of a prior processor which implemented all the key features
of SMT. There were some processors that implemented SMT, but they were
special purpose (ray tracing), lacking caches, etc. etc.

Why not look at the "micro"-architecture of the /195? The Dual I-
Stream isn't so much different. Two instructions streams from the
I-box being fed into the E-box so it had something to do if either
'I's took a branch.

So the idea is that on a long latency event, you switch to another
process or thread? This sounds like a precursor to switch on event
multithreading.

All together, it seems to me that the burden of proof rests upon your
shoulders to show:
1. What the 195 is.

WOW If you have to ask this, clearly you're not capable of
holding up your end of any such argument. ...not to mention the
/95.


2. That it actually implemented SMT

Do some more research. SMT, as you narrowly define it? Maybe not.
here is little new under the sun though. Perhaps you'd like to
follow Intel's SMT patents backwards?

The SMT research at UW clearly was influenced by prior efforts. They
cited quite a few of them in the paper I mentioned. I didn't see
anything on the 195 in their paper. Now perhaps the connection is 2nd
degree or 3rd degree. However, it seems to me that SMT likely focuses
on addressing different performance issues than what the 195 was faced
with. Are the ideas similar? Somewhat. But AFAICT they are quite
different beasts. It sounds like the dual istream is far more similar
to SoEMT than SMT.

DK

On 16 Dec 2006 17:49:19 -0800, "David Kanter" wrote:


Del Cecchi wrote:
David Kanter wrote:
Yousuf Khan wrote:

David Kanter wrote:

You heard Del say no such thing. I said there was a heated debate,
which is a long way from "huge fight". Back in the day there was honest
disagreement over the magnitude of the power and performance difference.

My apologies if I mischaracterized your statement. The point remains:
certain elements within IBM clearly did not believe that SOI was worth
it, and wanted to stick with bulk.

And SOI is not just being used for "high end stuff". It just isn't
being used for Standard Cell ASIC chips.

Perhaps our definition of high end vary...

SOI adds substantial costs, it would also force Intel to totally rework
their circuit stuff, etc. etc. And frankly, SOI is worth less and less
performance at every node.

Gee, I haven't heard that. Who told you that? Have you done
measurements? Run 3D field simulations? Or was this Intel spin?
Remember sometimes spin is true and sometimes it isn't.

This was information from an engineer in Canada who used to post to
comp.arch. I have no particular reason to disbelieve what he said,
although I'm certainly open to listening to other POVs. I believe I've
already indicated that I'm not an EE, physicist nor do I run sims. I
would point out that there is some information on the relative merits
of the different processes:

If you look back at what you posted, Intel is apparently considering SOI
for the 32nm and 22nm nodes. Ther appears to be a umm, dichotomy in your
reasoning here.

http://www.realworldtech.com/page.cf...005001504&p=14

This article, written by David Wang, shows a cross comparison of
different process technologies. In looking at the 65nm nodes, we can
compare the IBM process to the joint IBM/AMD/Toshiba/Sony. It appears
that the Ion for ITSA is slightly higher, while Intel's Ioff is about
2x lower. Of course, Intel's high Vt transistors have substantially
less leakage (factor of ~10) than the low Vt, at the cost of worse Ion
performance.

With all due respect to Dave Wang, somtime around the time of that article,
Dave stated categorically right in this NG that we would never see SOI 65nm
from Chartered... and now??

Sure, I can buy a cell phone for 20 dollars at walmart and it provides a
useful service to the average person, even in a LDC. What use is a PC
to the average person in a LDC?

It's a rather useful educational tool. Word processing, spread sheets,
email, wikipedia, developing. All sorts of things you can do.

From what I've observed, the most useful part of PCs/Internet for students
is as a tool for plagiarism...and theft.:-(

--
Rgds, George Macdonald

George Macdonald wrote:
On 16 Dec 2006 17:49:19 -0800, "David Kanter" wrote:


Del Cecchi wrote:

David Kanter wrote:

Yousuf Khan wrote:


David Kanter wrote:

You heard Del say no such thing. I said there was a heated debate,
which is a long way from "huge fight". Back in the day there was honest
disagreement over the magnitude of the power and performance difference.

My apologies if I mischaracterized your statement. The point remains:
certain elements within IBM clearly did not believe that SOI was worth
it, and wanted to stick with bulk.


And SOI is not just being used for "high end stuff". It just isn't
being used for Standard Cell ASIC chips.

Perhaps our definition of high end vary...


SOI adds substantial costs, it would also force Intel to totally rework
their circuit stuff, etc. etc. And frankly, SOI is worth less and less
performance at every node.

Gee, I haven't heard that. Who told you that? Have you done
measurements? Run 3D field simulations? Or was this Intel spin?
Remember sometimes spin is true and sometimes it isn't.

This was information from an engineer in Canada who used to post to
comp.arch. I have no particular reason to disbelieve what he said,
although I'm certainly open to listening to other POVs. I believe I've
already indicated that I'm not an EE, physicist nor do I run sims. I
would point out that there is some information on the relative merits
of the different processes:


If you look back at what you posted, Intel is apparently considering SOI
for the 32nm and 22nm nodes. Ther appears to be a umm, dichotomy in your
reasoning here.


http://www.realworldtech.com/page.cf...005001504&p=14

This article, written by David Wang, shows a cross comparison of
different process technologies. In looking at the 65nm nodes, we can
compare the IBM process to the joint IBM/AMD/Toshiba/Sony. It appears
that the Ion for ITSA is slightly higher, while Intel's Ioff is about
2x lower. Of course, Intel's high Vt transistors have substantially
less leakage (factor of ~10) than the low Vt, at the cost of worse Ion
performance.


With all due respect to Dave Wang, somtime around the time of that article,
Dave stated categorically right in this NG that we would never see SOI 65nm
from Chartered... and now??


Sure, I can buy a cell phone for 20 dollars at walmart and it provides a
useful service to the average person, even in a LDC. What use is a PC
to the average person in a LDC?

It's a rather useful educational tool. Word processing, spread sheets,
email, wikipedia, developing. All sorts of things you can do.


From what I've observed, the most useful part of PCs/Internet for students
is as a tool for plagiarism...and theft.:-(

And spread sheets and english word processing, english wikipedia, all
big help to joe dugan in LDC, eh?

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

George Macdonald wrote:
On 16 Dec 2006 17:49:19 -0800, "David Kanter" wrote:


Del Cecchi wrote:
David Kanter wrote:
Yousuf Khan wrote:

David Kanter wrote:

You heard Del say no such thing. I said there was a heated debate,
which is a long way from "huge fight". Back in the day there was honest
disagreement over the magnitude of the power and performance difference.

My apologies if I mischaracterized your statement. The point remains:
certain elements within IBM clearly did not believe that SOI was worth
it, and wanted to stick with bulk.

And SOI is not just being used for "high end stuff". It just isn't
being used for Standard Cell ASIC chips.

Perhaps our definition of high end vary...

SOI adds substantial costs, it would also force Intel to totally rework
their circuit stuff, etc. etc. And frankly, SOI is worth less and less
performance at every node.

Gee, I haven't heard that. Who told you that? Have you done
measurements? Run 3D field simulations? Or was this Intel spin?
Remember sometimes spin is true and sometimes it isn't.

This was information from an engineer in Canada who used to post to
comp.arch. I have no particular reason to disbelieve what he said,
although I'm certainly open to listening to other POVs. I believe I've
already indicated that I'm not an EE, physicist nor do I run sims. I
would point out that there is some information on the relative merits
of the different processes:

If you look back at what you posted, Intel is apparently considering SOI
for the 32nm and 22nm nodes. Ther appears to be a umm, dichotomy in your
reasoning here.

Not really. When I say SOI, I mean PD-SOI. Intel plans to use FD-SOI,
which is a rather different beast. No dichotomy there...

http://www.realworldtech.com/page.cf...005001504&p=14

This article, written by David Wang, shows a cross comparison of
different process technologies. In looking at the 65nm nodes, we can
compare the IBM process to the joint IBM/AMD/Toshiba/Sony. It appears
that the Ion for ITSA is slightly higher, while Intel's Ioff is about
2x lower. Of course, Intel's high Vt transistors have substantially
less leakage (factor of ~10) than the low Vt, at the cost of worse Ion
performance.

With all due respect to Dave Wang, somtime around the time of that article,
Dave stated categorically right in this NG that we would never see SOI 65nm
from Chartered... and now??

How does that matter? David's numbers can all be checked against the
IEDM presentations/papers AFAIK. The numbers say it all...

DK

Bet Rambus tries to stick thier little dicks in this too.

"YKhan" wrote in message
oups.com...
Only they call it floating-body RAM. AMD obviously has put a scare into
Intel with its well-advanced studies with Innovative Silicon. It would
be interesting to see how Intel can get around Innovative's patents in
this field. BTW, the "history effect" that Intel is talking about is
capacitance, and this indicates that Intel is looking into using SOI as
well, because this is the only way it can create a capacitance.

Intel talk up Floating Body Cells
http://www.theinquirer.net/default.aspx?article=36285

"don't look" wrote in message
news:Ssgmh.1571$IT2.121@trnddc06...
Bet Rambus tries to stick thier little dicks in this too.

"YKhan" wrote in message
oups.com...
Only they call it floating-body RAM. AMD obviously has put a scare
into
Intel with its well-advanced studies with Innovative Silicon. It would
be interesting to see how Intel can get around Innovative's patents in
this field. BTW, the "history effect" that Intel is talking about is
capacitance, and this indicates that Intel is looking into using SOI
as
well, because this is the only way it can create a capacitance.

Intel talk up Floating Body Cells
http://www.theinquirer.net/default.aspx?article=36285

There are always 6111778 and 5977578 to keep it interesting.

"Robert Redelmeier" wrote in message
. net...
Harrumphff! It seems you used some sort of "Global Search"
to find your name.

No, actually I subscribed to the group just today after many, many months of
not reading. I read a number of threaded conversations, and that
particular comment leapt out after reading another one with my name
mentioned.

The quote you lifted deep out of context
was Keith berating David in a long exchange a month ago.
AFAICS, "Dean" was a typo. But if the shoe fits ...

Actually, there was another post where Keith called David "Dean Jr". So
perhaps the 'shoe' that fits is not the one you think it is.


As for the ad-hominem, IMHO it was justified by David's
obdurancy. An attempt to shake his beliefs (P4 SMT) so he
could see. Not always adviseable or polite.

Being little more than a dressed-up P1, the dual issue P4 is
singularly ill-suited to SMT. It is too starved of issue
ports and only can run a thread without slowing the other
when one is stalled by RAM-fetch. Which admittedly is fairly
long with the poxy (high latency) Intel MCH architecture.

When people start claiming that personal attacks are justified, they've
simply bought into the bad behavior that has become all too prevalent here
and elsewhere. I am ashamed to admit that I was a part of the degradation
back during the John Corse years, and it changed the culture of this group
irreparably, IMO. I am very happy to see that Tony, yourself and several
others have refrained from succumbing to the behavior yourselves - but
accepting it and actually justifying it is troubling.

Nonetheless, the perusing of the group has done nothing to make me regret my
decision to stop reading/posting. I realize nobody else really cares
anyway, so enjoy the peace it brings...

Regards,
Dean


-- Robert