DRAM Questions

Hello all. This is my first post here.

First off I am not asking someone to do homework for me but to point
me in some direction towards answers. I am NEW to digital systems and
computer architecture. I have a question concerning the refresh
operations in DRAM technology.
I know that data stored in memory locations (cells, banks, etc.) can
be lost due to the transistor (acting as a cap) leaking, when memory
is read the data is lost and your basic noise problems.
It seems to me that if a certain memory location, bank, etc., needs to
be refreshed so that the data is not lost there is a "contradiction".
What I mean is that if some circuitry (i.e. the DRAM controller or
something) "knows" what to refresh that memory location to, why does
it need to be refreshed anyway? It seems to me that there is some
"magical or virtual memory" elsewhere that knows the data content of
the memory locations and can thus refresh that location to what it
was, and if that is so, why wouldn't a processor just read (maybe
write also) too this "magical or virtual memory" instead?
Is there some type of very good buffer that reads data from the memory
device (which destroys the data there) then puts the data on the bus
and then re-rewrites that data (the original data that is now stored
in itself) to the memory location from which it just read from (act of
refreshing)?
I know that there are reasons and explanations for this refresh
operation so I hope that I was clear in asking my question.

tia
JLD