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#1
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Intel's glued-together dual-cores
SiliconStrategies.com - Intel 'dual-core' could be two die glued
together, says report http://www.siliconstrategies.com/art...cleId=55301654 Quote:
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#2
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On 15 Dec 2004 08:28:44 -0800, "YKhan" wrote:
SiliconStrategies.com - Intel 'dual-core' could be two die glued together, says report http://www.siliconstrategies.com/art...cleId=55301654 Quote:
Hmmm, VIA talked along similar lines a month or so ago... calling it "twin core" IIRC. Rgds, George Macdonald "Just because they're paranoid doesn't mean you're not psychotic" - Who, me?? |
#3
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George Macdonald wrote:
Hmmm, VIA talked along similar lines a month or so ago... calling it "twin core" IIRC. Yup, Intel is racing to keep up against VIA. :-) Yousuf Khan |
#4
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On Thu, 16 Dec 2004 08:33:20 -0500, Yousuf Khan wrote:
George Macdonald wrote: Hmmm, VIA talked along similar lines a month or so ago... calling it "twin core" IIRC. Yup, Intel is racing to keep up against VIA. :-) Ouch! You're cruel! ;-) -- Keith |
#5
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YKhan wrote:
SiliconStrategies.com - Intel 'dual-core' could be two die glued together, says report http://www.siliconstrategies.com/art...cleId=55301654 Quote:
Quote:
There are a lot of interesting questions about this coming technology, it could be really neat or it could be a true cob job. -- bill davidsen ) SBC/Prodigy Yorktown Heights NY data center Project Leader, USENET news http://newsgroups.news.prodigy.com |
#6
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On 15 Dec 2004 08:28:44 -0800, "YKhan" wrote:
SiliconStrategies.com - Intel 'dual-core' could be two die glued together, says report http://www.siliconstrategies.com/art...cleId=55301654 [quote]LONDON - The planned dual-core processor from Intel Corp. known as Smithfield could start out as two Pentium 4 chips in a single package, according to a report that appeared online Tuesday (Dec 14.). According to the report in The Register, which appeared as Intel held a telephone press conference to discuss its dual-core processor which is expected to ship mid-2005, a company executive did not deny the suggestion that Smithfield would be based on two Pentium 4 processors glued together in a single package. ....snip... I already have an oil-filled electric heater that has dual (600 W and 900W) core. The cores can be turned on separately or together, thus providing 3 heating levels. Is Intel-branded dual-core P4 space heater going to have the same feature, i.e. could one of the cores be turned off when it gets too hot in the room? ;-) |
#7
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Bill Davidsen wrote:
I believe the original PentiumPro was two chips in a single die carrier, the CPU and the cache. Yes, and I would guess that the current production Xeons with L3 caches are also similar, with the L3 being a separate chip? To the point, are these current production compatible P4 (ie. HT enabled)? And do they share L2 (or L3) cache? No, they don't share any of their caches with each other. Actually, the AMD dual-cores are going to be similar to this too, with no shared cache. You lose a lot of cost savings at the very least, by not integrating the L2 caches. But you might get slightly better performance by having the dedicated L2's. There are a lot of interesting questions about this coming technology, it could be really neat or it could be a true cob job. I think the main question is whether the internal CPU-CPU communications mechanism is properly designed or just cobbled together. A properly designed one would reduce if not eliminate entirely the amount of cache-snoop traffic going over the FSB. Yousuf Khan |
#8
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"Yousuf Khan" wrote in message ... No, they don't share any of their caches with each other. Actually, the AMD dual-cores are going to be similar to this too, with no shared cache. You lose a lot of cost savings at the very least, by not integrating the L2 caches. But you might get slightly better performance by having the dedicated L2's. Yousuf Khan Interesting, I thought that the DC Opterons were going to share their L2. I could have sworn I saw that in one of their presentations. Carlo |
#9
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On Sat, 18 Dec 2004 12:20:53 -0500, Yousuf Khan
wrote: Bill Davidsen wrote: I believe the original PentiumPro was two chips in a single die carrier, the CPU and the cache. Yes, and I would guess that the current production Xeons with L3 caches are also similar, with the L3 being a separate chip? Actually no, all integrated on-die. The L3 just has a narrower (64-bit vs. 256-bit) connection to the processor core and higher latency when compared to the L2 cache. Same goes for Itaniums. To the point, are these current production compatible P4 (ie. HT enabled)? And do they share L2 (or L3) cache? No, they don't share any of their caches with each other. Actually, the AMD dual-cores are going to be similar to this too, with no shared cache. You lose a lot of cost savings at the very least, by not integrating the L2 caches. But you might get slightly better performance by having the dedicated L2's. It probably also simplifies design by a fair bit. A shared cache is going to be trickier to design than a separate one. By no means an insurmountable problem, but it would probably just compound add to the performance hit, making it not worthwhile. Besides which we seem to be quickly getting to a point where designers have more transistors than they can figure out what to do with. ------------- Tony Hill hilla underscore 20 at yahoo dot ca |
#10
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Carlo Razzeto wrote:
Interesting, I thought that the DC Opterons were going to share their L2. I could have sworn I saw that in one of their presentations. Nope, and you'll notice that DC Opterons are almost exactly twice the size of their SC versions. That's cause they not only add an extra core, they also added the whole L2 cache too. From what I've heard, AMD did indeed make their Opterons DC-capable right from the beginning, but what that actually meant was that they had simply designed the core so that if they cut two cores side-to-side, they would see communications channels directly aligned up on each die. So they were actually ever planning on sharing caches with each other. Yousuf Khan |
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