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how can a newer processor have worse L1 cache?
On 4/6/2011 9:17 AM, Anne Onime wrote:
I have seen many peoples castigating the Prescott compared to the Northwood P4. We had a stretch of rainy days, so I tested some old PCs - I had a draw full of Pentium IVs to swap in them. One benchmark for L1 latency came out thus: Northwood 2 cycles Prescott 5 cycles Cedar Mill 4 cycles How did Intel bugger up the L1 cache? In order to get a really knowledgeable answer to this question, you should ask it in comp.arch. In order *really* to understand the difficulty and criticality of L1 latency trades, I think you'd actually have to design a microprocessor, something that most of us will never get a chance to do, except possibly as a homebrew toy project. Robert. |
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