ixf440's MDC/MDIO communiction while packets are transceived.

Hi.

I'm woring with an Intel IXP1240(Network Processor), IXF440(8 port
MAC), and two LXT9763(PHY). I met a problem : While data packets are
being transceived, if I try MDC/MDIO serial communiction of IXF440 to
LXT9763, tx-error counter of IXF440 is increased. I don't understand
why MDC/MDIO communication interferes with data communication. Any
experiece and information are welcome.

Thanks for any ideas.

Hi Winam,

We used the IXF440 in our last project so I'm a little bit familiar with
it. If You take a look at side 21 of the manual (revision 004) at the
point 3.1.1 You will find:

"The configuration and the serial registers are writable only when the
port is in stop state (as
reported in the interrupt status register – INT_STT), following transmit
and receive disable
programming."

Maybe this is your problem.


Regards
Michael


Winam wrote:
Hi.

I'm woring with an Intel IXP1240(Network Processor), IXF440(8 port
MAC), and two LXT9763(PHY). I met a problem : While data packets are
being transceived, if I try MDC/MDIO serial communiction of IXF440 to
LXT9763, tx-error counter of IXF440 is increased. I don't understand
why MDC/MDIO communication interferes with data communication. Any
experiece and information are welcome.

Thanks for any ideas.