L1/L2 cache question

John F. Carr wrote:

In article ,
Jon Beniston wrote:

| L1, traditionally, is split, because you get better performance if you
| can fetch an instruction and some data in the same cycle. Its probably
| easier/faster to have split caches than a multi-ported cache.

Also, instruction caches are typically read-only.

Ahh, non-refillable caches, you might want to get a patent on that..


Sounds like the mask-programmed ROM on old microcontrollers.
It's been over 20 years; you can use the idea for free.

It sounds even more like the CPU microcode ROM.

Since this avoided having to load the microcode from paper tape, it was
indeed a form of cache, right?

Terje

--
-
"almost all programming can be viewed as an exercise in caching"

In article ,
(Iain McClatchie) wrote:

| Jan Other observation: There are several implementations on the market that
| Jan will fetch some data from L2 only (FP, in the cases I know)
|
| Which implementations? I know of
|
| MIPS R8000
| Itanium (#1, that I know of)
|
| Do you know of others?

The Intrinsity FastMATH processor (MIPS core, 16/32-way SIMD matrix
coprocessor) -- coprocessor accesses are directly to the L2 (but
coherent with the L1).

-- tim

In article ,
Jan C. =?iso-8859-1?Q?Vorbr=FCggen?= wrote:

... one could imagine situations where there is no L1 D cache.

HyperSPARC has on-chip I-cache only and off chip unified L2 cache

Tera (CRAY) MTA has a large I-cache and no D-cache

--
John Carr )

The Intrinsity FastMATH processor (MIPS core, 16/32-way SIMD matrix
coprocessor) -- coprocessor accesses are directly to the L2 (but
coherent with the L1).

-- tim

Are you at Intrinisity, Tim Olson?
I was wondering...

In article ,
"Andy Glew" wrote:

| The Intrinsity FastMATH processor (MIPS core, 16/32-way SIMD matrix
| coprocessor) -- coprocessor accesses are directly to the L2 (but
| coherent with the L1).
|
| -- tim
|
| Are you at Intrinisity, Tim Olson?
| I was wondering...


Yes, perhaps I should have mentioned that in my original post...

-- tim