Tyan Thunder K8W Questions

"spinlock" wrote in message
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wrote in message
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spinlock wrote:
First, there is no "inter-processor" traffic.

All multi-cpu systems have inter-processor traffic, otherwise the
different CPUs would not be connected, right?

WRONG!

Threads executuing on the different processors communicate with
each other through control structures, like spinlocks, in memory.

THERE ARE NO x86 intsructions that read or write another
processor.

Everything is orchestrated through memory accesses.

Umm, you are *SERIOUSLY* confused and, I hope you don't take offense at
this, can't possibly have any understanding *at all* of how multiprocessor
machines work in the real world. The FSB (or HT link in a 2-CPU Opteron
system) is just filled with MESI (cache coherency) traffic between the two
processors. I think you're forgetting that the vast majority of processor
memory accesses actually take places in the caches, what are physically
located inside the CPU package.

DS

WRONG!

I don't know how AMD's kludge works, but, Intel processors
snoop the bus and they see the other processors memory writes
and act accordingly.

No cache coherency data/metadata/anything is sent between processors.

PS I never take offence when unarmed people start flame wars.

"David Schwartz" wrote in message
...

"spinlock" wrote in message
...

wrote in message
...
spinlock wrote:
First, there is no "inter-processor" traffic.

All multi-cpu systems have inter-processor traffic, otherwise the
different CPUs would not be connected, right?

WRONG!

Threads executuing on the different processors communicate with
each other through control structures, like spinlocks, in memory.

THERE ARE NO x86 intsructions that read or write another
processor.

Everything is orchestrated through memory accesses.

Umm, you are *SERIOUSLY* confused and, I hope you don't take offense
at
this, can't possibly have any understanding *at all* of how multiprocessor
machines work in the real world. The FSB (or HT link in a 2-CPU Opteron
system) is just filled with MESI (cache coherency) traffic between the two
processors. I think you're forgetting that the vast majority of processor
memory accesses actually take places in the caches, what are physically
located inside the CPU package.

DS