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AMD has the answer for Intel
On Mon, 29 Sep 2003 13:39:39 -0500, Ed wrote:
Fast forward a decade or two, and some might say Intel is one bit short of a byte. Itanium, its 64-bit processor, is selling slowly however you count it. Like all chip manufacturers, Intel does not give out its own figures, but luckily for us AMD is more than happy to oblige, and estimates Intel has shipped around 16,000 of its 64-bit chips. Now you can add a few to compensate for AMD's negative spin, remove a few for the ones that Intel shipped gratis, and divide by four to get a figure that represents the total number of servers out there (few are single-processor servers) using Itanium. It's not very impressive by any measure. http://zdnet.com.com/2100-1107_2-5083279.html A touch off-topic for the main thrust of this article, but did you read this paragraph? : "Now compare AMD's approach. AMD appeared on the mainstream computing scene in the early 90s with its own reverse-engineered version of the 386. After a bumpy ride through the mid-90s, caused largely by the decision to forward-engineer its version of the 486, AMD emerged with the Athlon and now the Athlon 64--its own 64-bit processor." OUCH! Can you say "not doing your research"? AMD appeared on the mainstream computing scene in the early '80s when they were a second source for Intel's 8086 and 8088 used in the original PC. They were founded only 6 months after Intel and had many products of their own before the PC deal. And then AMD made a "decision" to design their own 486 chip? I'd hardly call being taken to court a "decision" that AMD made! Besides which they only released their in-house design 486 chip (the 5x86) a couple years after they had released the AMD486 that was reverse engineered from Intel. The 5x86 was a pretty successful chip too, it was what followed (the K5) that caused them a lot of pain. Of course, then the article goes on to say that the Athlon64 is really like a modern 386SX, which "which had a 16-bit heart but 32-bit addressing"?!?! A 16-bit heart?! Since when is a data bus the "heart" of the processor? And just how does this in any way relate to the Opteron/Athlon64, with it's integrated memory controller and hypertransport I/O connections? The article specifically goes on to say "Sure, AMD's chips are not true 64-bit in the same sense that the 386sx was not true 32-bit." WTF?! What is this guy smoking! The 386SX was very much a 32-bit processor, it just happened to be saddled by a 16-bit data bus. The Athlon64 and Opteron are in EVERY sense of the word a 64-bit processor. No ifs, ands or buts about it. ------------- Tony Hill hilla underscore 20 at yahoo dot ca |
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"Tony Hill" wrote in message
.com... http://zdnet.com.com/2100-1107_2-5083279.html A touch off-topic for the main thrust of this article, but did you read this paragraph? : "Now compare AMD's approach. AMD appeared on the mainstream computing scene in the early 90s with its own reverse-engineered version of the 386. After a bumpy ride through the mid-90s, caused largely by the decision to forward-engineer its version of the 486, AMD emerged with the Athlon and now the Athlon 64--its own 64-bit processor." OUCH! Can you say "not doing your research"? AMD appeared on the mainstream computing scene in the early '80s when they were a second source for Intel's 8086 and 8088 used in the original PC. They were founded only 6 months after Intel and had many products of their own before the PC deal. And then AMD made a "decision" to design their own 486 chip? I'd hardly call being taken to court a "decision" that AMD made! Besides which they only released their in-house design 486 chip (the 5x86) a couple years after they had released the AMD486 that was reverse engineered from Intel. The 5x86 was a pretty successful chip too, it was what followed (the K5) that caused them a lot of pain. I think AMD had a blind-room microcode that they were working on for their 486, just in case they lost the Intel lawsuit, otherwise the AMD 486's were exact replicas of the Intel ones, right down to the same erratas. I don't know if AMD ever used the blind-room microcode, but I think they did. Back then avoiding a lawsuit was as simple as changing the microcode. I think they adopted their own microcode designs once Intel introduced the CPUID command with the "GenuineIntel" strings in them, which AMD obviously couldn't copy, so they got the "AuthenticAMD" strings. Of course, then the article goes on to say that the Athlon64 is really like a modern 386SX, which "which had a 16-bit heart but 32-bit addressing"?!?! A 16-bit heart?! Since when is a data bus the "heart" of the processor? And just how does this in any way relate to the Opteron/Athlon64, with it's integrated memory controller and hypertransport I/O connections? The article specifically goes on to say "Sure, AMD's chips are not true 64-bit in the same sense that the 386sx was not true 32-bit." WTF?! What is this guy smoking! The 386SX was very much a 32-bit processor, it just happened to be saddled by a 16-bit data bus. The Athlon64 and Opteron are in EVERY sense of the word a 64-bit processor. No ifs, ands or buts about it. Yeah, I noticed this too, but then I immediately forgave this blunder when I considered the source of the article, ZDNet, the PCMag people. You can't expect ZDNet to give you completely accurate information. Don't they have it in their charter that they don't guarantee anything that they say is in anyway similar to the truth? I don't I thought I read that somewhere. :-) Yousuf Khan |
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On Mon, 29 Sep 2003 22:07:35 +0000, Tony Hill wrote:
The article specifically goes on to say "Sure, AMD's chips are not true 64-bit in the same sense that the 386sx was not true 32-bit." WTF?! What is this guy smoking! The 386SX was very much a 32-bit processor, it just happened to be saddled by a 16-bit data bus. The Athlon64 and Opteron are in EVERY sense of the word a 64-bit processor. No ifs, ands or buts about it. I just want to make this very clear. Before Intel/Ibm marketing got into the picture, cpu's bit size was rated by the data bus. Original data sheets from Intel show the 8088 as an 8 bit cpu, even though it had 16bit registers. The Motorola 68000 was also designated as a 16bit cpu even though it had 32bit registers. Once marketing got into the picture everything changes. That's why all the confusion on the P4/Athlon FSB speeds. Just keep letting them get away with this crap and take it. Pretty soon you won't know wtf you're buying. IFAIC, the 386SX was the worst piece of **** ever produced and I know many of people that bought them thinking they were buying 386 speeds when what they got was really 286 speeds. -- Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB) http://mysite.verizon.net/res0exft/cpu.html |
#4
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On Tue, 30 Sep 2003 07:44:00 GMT, "Wes Newell"
wrote: On Mon, 29 Sep 2003 22:07:35 +0000, Tony Hill wrote: The article specifically goes on to say "Sure, AMD's chips are not true 64-bit in the same sense that the 386sx was not true 32-bit." WTF?! What is this guy smoking! The 386SX was very much a 32-bit processor, it just happened to be saddled by a 16-bit data bus. The Athlon64 and Opteron are in EVERY sense of the word a 64-bit processor. No ifs, ands or buts about it. I just want to make this very clear. Before Intel/Ibm marketing got into the picture, cpu's bit size was rated by the data bus. Why in the hell would anyone do that?!?! That's about the dumbest way I can think of to compare the bit-ness of a CPU! So the Pentium was a 64-bit processor, as are all current PC chips except for the Athlon64, which is now a... umm.. what do you call the Athlon64 which doesn't have a data bus? A 0-bit processor? Or perhaps it's a dual-processor 16-bit unidirectional chip because it has two 16-bit unidirectional hypertransport links? What the heck does that make the Opteron then? Good thing IBM has their 1024 bit chips these days. Original data sheets from Intel show the 8088 as an 8 bit cpu, even though it had 16bit registers. The Motorola 68000 was also designated as a 16bit cpu even though it had 32bit registers. Once marketing got into the picture everything changes. Sounds to me more like a question of people finally getting smacked over the head with a clue. Who the hell cares what the width of the data bus is? That's why all the confusion on the P4/Athlon FSB speeds. Just keep letting them get away with this crap and take it. Pretty soon you won't know wtf you're buying. IFAIC, the 386SX was the worst piece of **** ever produced and I know many of people that bought them thinking they were buying 386 speeds when what they got was really 286 speeds. Back in the day when I was still a young'un living at home, my parents had a 386SX. Yes, it had it's ups and it's downs, and in retrospect we probably would have been better off spending a bit more for a 386DX, but the thing worked and was a hell of a lot faster than the XT it replaced. The chip was definitely a 32-bit chip though, it ran pretty much all 32-bit software I threw at it, albeit sometimes at rather slow speeds. I remember being HUGELY disappointed when Doom came out and the performance stank on this PC. A bit of a rip-off? Perhaps. The worst piece of **** ever produced? I think that might be stretching it. There's been a LOT of **** produced over the years! ------------- Tony Hill hilla underscore 20 at yahoo dot ca |
#5
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On Tue, 30 Sep 2003 13:08:38 +0000, Tony Hill wrote:
On Tue, 30 Sep 2003 07:44:00 GMT, "Wes Newell" wrote: On Mon, 29 Sep 2003 22:07:35 +0000, Tony Hill wrote: The article specifically goes on to say "Sure, AMD's chips are not true 64-bit in the same sense that the 386sx was not true 32-bit." WTF?! What is this guy smoking! The 386SX was very much a 32-bit processor, it just happened to be saddled by a 16-bit data bus. The Athlon64 and Opteron are in EVERY sense of the word a 64-bit processor. No ifs, ands or buts about it. I just want to make this very clear. Before Intel/Ibm marketing got into the picture, cpu's bit size was rated by the data bus. Why in the hell would anyone do that?!?! That's about the dumbest way I can think of to compare the bit-ness of a CPU! Because it made sense. Dive into the history of processors and you'll understand why. It was the bottleneck of the system. The cpu can't process data it doesn't have yet. That's why it went from a 4bit beginning to what it is today. Look at all the ways they speed this up with caches. Disable all your cpu caches and watch the most powerful cpu come to a crawl running over the data bus. A hybrid like the 8088 had to make 2 complete data cycles to get the same data a true 16bit cpu did in 1. But all this has become skewed by the marketing types. Bus speeds have always been measured in clock cycles. Now the marketing idiots decided to define the bus by the data rate, but using the clock speed unit of measure (MHz) instead of the data rate unit of measure (Bps, bps). Why? Simple because it looks better, and the majority of the people don't know it's just BS. So the Pentium was a 64-bit processor, as are all current PC chips except for the Athlon64, which is now a... umm.. what do you call the Athlon64 which doesn't have a data bus? A 0-bit processor? Or perhaps it's a dual-processor 16-bit unidirectional chip because it has two 16-bit unidirectional hypertransport links? What the heck does that make the Opteron then? To be honest, I haven't looked at the architecture that much. From what I can tell, the data comes across the HTL, which is 72 bits wide. with the Opteron/64FX having 2 of them for 144bits. Thus the much improved throughput of data to the core, and also why the regular A64 is quite a bit slower than the FX/Opteron series. Good thing IBM has their 1024 bit chips these days. Original data sheets from Intel show the 8088 as an 8 bit cpu, even though it had 16bit registers. The Motorola 68000 was also designated as a 16bit cpu even though it had 32bit registers. Once marketing got into the picture everything changes. Sounds to me more like a question of people finally getting smacked over the head with a clue. Who the hell cares what the width of the data bus is? Answered above. That's why all the confusion on the P4/Athlon FSB speeds. Just keep letting them get away with this crap and take it. Pretty soon you won't know wtf you're buying. IFAIC, the 386SX was the worst piece of **** ever produced and I know many of people that bought them thinking they were buying 386 speeds when what they got was really 286 speeds. Back in the day when I was still a young'un living at home, my parents had a 386SX. Yes, it had it's ups and it's downs, and in retrospect we probably would have been better off spending a bit more for a 386DX, but the thing worked and was a hell of a lot faster than the XT it replaced. Of course it was faster. The XT had an 8 bit data bus and the SX had a 16bit data bus.:-) The chip was definitely a 32-bit chip though, it ran pretty much all 32-bit software I threw at it, albeit sometimes at rather slow speeds. I remember being HUGELY disappointed when Doom came out and the performance stank on this PC. It was a 32bit cpu only in the sense that that's what Intel designated it. It was never considered a true 32bit cpu back then. A bit of a rip-off? Perhaps. The worst piece of **** ever produced? I think that might be stretching it. There's been a LOT of **** produced over the years! True.:-) Probably the absolute worst was the 486SLC. It only had a 16bit data bus too. They double screwed the people that bought these.:-) -- Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB) http://mysite.verizon.net/res0exft/cpu.html |
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On Tue, 30 Sep 2003 22:10:23 GMT, "Wes Newell"
wrote: On Tue, 30 Sep 2003 13:08:38 +0000, Tony Hill wrote: Why in the hell would anyone do that?!?! That's about the dumbest way I can think of to compare the bit-ness of a CPU! Because it made sense. Dive into the history of processors and you'll understand why. It was the bottleneck of the system. The cpu can't process data it doesn't have yet. That's why it went from a 4bit beginning to what it is today. Look at all the ways they speed this up with caches. Disable all your cpu caches and watch the most powerful cpu come to a crawl running over the data bus. A hybrid like the 8088 had to make 2 complete data cycles to get the same data a true 16bit cpu did in 1. But all this has become skewed by the marketing types. Bus speeds have always been measured in clock cycles. That was all well and good when we were talking about 1 vs. 2 clock cycles, but those days are LONG since past (for better or for worse). Measuring a bus by it's data rate is in no way marketing, it's the only worthwhile way to measure a bus! Would you prefer a P4 bus that is "somewhere in the 70 to 350 clock cycle range" description? How does that even begin to remotely help anyone?! Now the marketing idiots decided to define the bus by the data rate, but using the clock speed unit of measure (MHz) instead of the data rate unit of measure (Bps, bps). Why? Simple because it looks better, and the majority of the people don't know it's just BS. Most even semi-remotely technical info about processor specs lists both the clock speed of the bus and the bandwidth, and that's for desktop processors. The clock speed (or at least effective clock speed with today's double and quad data rate buses) has been ok for the PC world since we've had 64-bit buses on every system for nearly 10 years now. Of course, AMD had to go and screw all this up with their Athlon64 and Opteron : So the Pentium was a 64-bit processor, as are all current PC chips except for the Athlon64, which is now a... umm.. what do you call the Athlon64 which doesn't have a data bus? A 0-bit processor? Or perhaps it's a dual-processor 16-bit unidirectional chip because it has two 16-bit unidirectional hypertransport links? What the heck does that make the Opteron then? To be honest, I haven't looked at the architecture that much. From what I can tell, the data comes across the HTL, which is 72 bits wide. Umm, huh? HTL = Hypertransport Link? If so, it's 32-bits wide, 16-bits in each direction. with the Opteron/64FX having 2 of them for 144bits. Thus the much improved throughput of data to the core, and also why the regular A64 is quite a bit slower than the FX/Opteron series. I think you're confusing it's integrated memory controller with the hypertransport link. Which is your "data bus"? At best this is only slightly confusing in a single processor system, where you have memory requests coming over one bus and all other I/O going over a single hypertransport link. On multiprocessor systems, this gets MUCH worse, as your memory could be local (going over your own memory bus) or remote (going over a hypertransport link). Does a two-processor Opteron system then become a 256-bit chip (2 memory buses, each 128-bits wide), a 288-bit chip (2 memory buses, 128+16 bits for ECC), a 160-bit (128+16 local memory + 16-bits for HT), 176-bits (128+16 local memory and 16+16 for the bi-directional hypertransport)?! Face it, defining the bit-ness of a chip by the width of the data bus makes absolutely NO sense at all in this day and age! The Athlon64 and Opteron are 64-bit chips because: 1. They have 64-bit integer registers 2. They use 64-bit address pointers and address registers, program counter, etc. That's how everyone defines the bit-ness of CPUs, and that's the way it should be. Sounds to me more like a question of people finally getting smacked over the head with a clue. Who the hell cares what the width of the data bus is? Answered above. Great, maybe 20 years ago this made some sense, but not anymore. ------------- Tony Hill hilla underscore 20 at yahoo dot ca |
#7
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"Tony Hill" wrote in message
.com... On Tue, 30 Sep 2003 22:10:23 GMT, "Wes Newell" wrote [...] Now the marketing idiots decided to define the bus by the data rate, but using the clock speed unit of measure (MHz) instead of the data rate unit of measure (Bps, bps). Why? Simple because it looks better, and the majority of the people don't know it's just BS. Most even semi-remotely technical info about processor specs lists both the clock speed of the bus and the bandwidth, and that's for desktop processors. The clock speed (or at least effective clock speed with today's double and quad data rate buses) has been ok for the PC world since we've had 64-bit buses on every system for nearly 10 years now. Of course, AMD had to go and screw all this up with their Athlon64 and Opteron : Possibly I'm reading you wrong, but the thing about the "800 mhz FSB" and stuff is that it's NOT an 800MHz effective FSB. It's actually equvalent to a 200MHz 256-bit wide FSB in the case of QDR and 400MHz 128-bit wide in the case of DDR (substitute numbers to fit your system). There is a significant difference in performance between these two, especially when it comes to non-sequential data access (due to the difference in clock speed), but there's no difference in the data rate. In fact, DDR333 as marketiods like to call it can in some applications (non-sequential access on large datasets) beat QDR533. So calling the data rate the clock speed is just plain wrong. However, QDR will (generally speaking again) beat DDR at the same frequency, so there really needs to be two things advertised about the FSB: the signalling mechanism and the clock speed (NOT the signalling mechanism and the data rate as it is now). So "266MHz DDR" would become "133 MHz DDR'd" and "533MHz QDR" would become "133 MHz QDR'd". In the case of the Athlon 64, though, it gets a little more complex with two different external interfaces to the CPU. Not sure of the easiest way to fix that [...] -- Michael Brown www.emboss.co.nz : OOS/RSI software and more Add michael@ to emboss.co.nz - My inbox is always open |
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On Wed, 01 Oct 2003 06:51:23 +0000, Tony Hill wrote:
Measuring a bus by it's data rate is in no way marketing, it's the only worthwhile way to measure a bus! It is when the bus speed is 200MHz DDR or QDR but you call it 400MHz or 800MHz, when it isn't. Would you prefer a P4 bus that is "somewhere in the 70 to 350 clock cycle range" description? How does that even begin to remotely help anyone?! I prefer that when they talk about bus speeds that they follow excepted practices and give the real speed. I can determine the the data rate from that. A simple 200MHz DDR or 200MHz QDR would be fine. Most even semi-remotely technical info about processor specs lists both the clock speed of the bus and the bandwidth, and that's for desktop processors. The clock speed (or at least effective clock speed with today's double and quad data rate buses) Both the P4 and Athlon now have a 200MHz FSB. Anything higher than that is overclocked. There's no 400MHz FSB and no 800MHz fsb. Effective? Compared to what? The P4 isn't an effective fsb of 800MHz if you compare it to the Athlon FSB now is it? It's only effective 400MHz. Just another reason the effective arguement is BS unless it's fully explained what it's compared to. Yeah, I know, you know, but believe me, 90% of the people don't. And that's why it's marketing BS. has been ok for the PC world since we've had 64-bit buses on every system for nearly 10 years now. 10 years? It only started with the Athlon and P4. Prior to that all x86 cpu's had only one data bit per clock cycle. So the Pentium was a 64-bit processor, as are all current PC chips So if the P4 is a 64bit cpu, why won't it run a 64bit OS? except for the Athlon64, which is now a... umm.. what do you call the Athlon64 which doesn't have a data bus? A 0-bit processor? Or perhaps it's a dual-processor 16-bit unidirectional chip because it has two 16-bit unidirectional hypertransport links? What the heck does that make the Opteron then? To be honest, I haven't looked at the architecture that much. From what I can tell, the data comes across the HTL, which is 72 bits wide. Umm, huh? HTL = Hypertransport Link? If so, it's 32-bits wide, 16-bits in each direction. with the Opteron/64FX having 2 of them for 144bits. Thus the much improved throughput of data to the core, and also why the regular A64 is quite a bit slower than the FX/Opteron series. I think you're confusing it's integrated memory controller with the hypertransport link. Which is your "data bus"? At best this is only slightly confusing in a single processor system, where you have memory requests coming over one bus and all other I/O going over a single hypertransport link. On multiprocessor systems, this gets MUCH worse, as your memory could be local (going over your own memory bus) or remote (going over a hypertransport link). You're right. It's the data bus that's 72bits wide on the A64, and 144bits on the Opteron/FX. Don't know what i was thinking. Face it, defining the bit-ness of a chip by the width of the data bus makes absolutely NO sense at all in this day and age! The Athlon64 and Opteron are 64-bit chips because: 1. They have 64-bit integer registers 2. They use 64-bit address pointers and address registers, program counter, etc. So why does the Opteron/FX cpu's blow away the A64's at the same clock speed if the data bus doesn't mean anything? That's the only difference between them. -- Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB) http://mysite.verizon.net/res0exft/cpu.html |
#9
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Tony Hill wrote:
That was all well and good when we were talking about 1 vs. 2 clock cycles, but those days are LONG since past (for better or for worse). Measuring a bus by it's data rate is in no way marketing, it's the only worthwhile way to measure a bus! Would you prefer a P4 bus that is "somewhere in the 70 to 350 clock cycle range" description? How does that even begin to remotely help anyone?! I agree... but using MHz it's confusing. A DDR bus clocked at 200MHz is fine. Calling it a 400MHz bus is confusing... it is neither data rate (which would be in bits per second) nor the clock. It's about time that the marketing types got a clue. How many times have people come here and asked why they can't set their ram to 400MHz or some other rediculous question? Most even semi-remotely technical info about processor specs lists both the clock speed of the bus and the bandwidth, and that's for desktop processors. You need to know 3 of: clock speed, number of transfers per clock, bus width and bandwidth. The clock speed (or at least effective clock speed with today's double and quad data rate buses) Clock speed is clock speed, regardless of the number of transfers that happen per clock. Ben -- I'm not just a number. To many, I'm known as a String... |
#10
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On Tue, 30 Sep 2003 22:10:23 GMT, "Wes Newell"
wrote: Now the marketing idiots decided to define the bus by the data rate, but using the clock speed unit of measure (MHz) instead of the data rate unit of measure (Bps, bps). Why? Simple because it looks better, and the majority of the people don't know it's just BS. Clueless. |
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