AMD Athlon 64 3200+ vs Pentium 4 3.2ghz

On Sun, 12 Sep 2004 15:43:26 -0400, JK wrote:

I am very interested in that computer. It must be a very new model,
as the Athlon 64 3200+ at a 2 ghz clock speed is a chip made on
the new 90 nm process, and uses two on chip memory controllers,
and the newer socket 939 motherboard.

Naaah.. Nothing that exciting. Check the tech specs:

http://h20195.www2.hp.com/search/pdf...ad81ca315d.pdf

It's just a plain, old 130nm, 2.0GHz/1MB L2 cache, socket 754
Athlon64.

This website indicates
an October release for the chip. Is that system in stores already
(if so what country?),

The system seems to only be sold in Britain, though I'm sure that HP
has similar systems available in other countries.

or is it a built to order system to be shipped
in a week or two? I couldn't find information on the net under that
model number.

http://www.c627627.com/AMD/Athlon64/

You'll notice on that chart that there are three different Athlon64
3200+ chips. The one used in this system is the first, a "Clawhammer"
running at 2.0GHz with 1MB of L2 cache and socket 754. The
"Newcastle" running at 2.2GHz and with 512KB of L2 cache and socket
754 is also available now (though the chart has a typo on the date, it
came out in April of 2004, not April of 2003). The chip you're
thinking of, a socket 939 "Winchester" running at 2.0GHz and 512KB of
L2 cache won't be out for a little bit.

-------------
Tony Hill
hilla underscore 20 at yahoo dot ca

JK wrote:

I am very interested in that computer. It must be a very new model,
as the Athlon 64 3200+ at a 2 ghz clock speed is a chip made on the
new 90 nm process, and uses two on chip memory controllers, and the
newer socket 939 motherboard.

JK,

Why would dual channel imply two memory controllers?

--
Regards, Grumble

On Mon, 13 Sep 2004 12:09:43 +0200, Grumble wrote:

JK wrote:

I am very interested in that computer. It must be a very new model,
as the Athlon 64 3200+ at a 2 ghz clock speed is a chip made on the
new 90 nm process, and uses two on chip memory controllers, and the
newer socket 939 motherboard.

JK,

Why would dual channel imply two memory controllers?

Imply? Dual channel == two memory controllers.

--
Keith

On Sun, 12 Sep 2004 20:08:23 +0100, GSV Three Minds in a Can wrote:

Bitstring , from the wonderful person JK
said
snip

It was only when I got home, I learnt that 3200+ doesn't mean 3.2ghz and
that this processor is actually 2.0ghz.

The clock speed doesn't matter. What matters is how fast it runs programs.

http://www.anandtech.com/cpuchipsets...spx?i=2065&p=6

Think of the clock speed of a processor as being like how many steps
per minute an animal makes.

I prefer 'the rev counter in your car'. Yeah, it measures something, but
nothing you really care about comparing between different brands.

Exactly. If you're spinning your wheels, all you're doing is wasting
energy. ;-)

Roadspeed and gas consumption are much more interesting.

....not to mention negotiating curves.

--
Keith

keith wrote:

Grumble wrote:

Why would dual channel imply two memory controllers?

Imply? Dual channel == two memory controllers.

Can't a dual-channel memory controller be implemented as one circuit
with twice as many wires as a single-channel memory controller?

--
Regards, Grumble

On Tue, 14 Sep 2004 14:30:11 +0200, Grumble wrote:

keith wrote:

Grumble wrote:

Why would dual channel imply two memory controllers?

Imply? Dual channel == two memory controllers.

Can't a dual-channel memory controller be implemented as one circuit
with twice as many wires as a single-channel memory controller?

An unqualified *no*. It would be more difficult, slower, and add nothing
to the mix. One of the reasons to go with multiple channels is to
simplify timing across many wires. Note the high-speeed interfaces have
narrower "channels" so the timing is simpler (or possible). Indeed, the
ApplePI/EI bus has timing adjustments on a per-pin basis. Making channels
wider makes no sense.

--
Keith

On Thu, 16 Sep 2004 22:40:36 -0400, keith wrote:

On Tue, 14 Sep 2004 14:30:11 +0200, Grumble wrote:

keith wrote:

Grumble wrote:

Why would dual channel imply two memory controllers?

Imply? Dual channel == two memory controllers.

Can't a dual-channel memory controller be implemented as one circuit
with twice as many wires as a single-channel memory controller?

An unqualified *no*. It would be more difficult, slower, and add nothing
to the mix. One of the reasons to go with multiple channels is to
simplify timing across many wires. Note the high-speeed interfaces have
narrower "channels" so the timing is simpler (or possible). Indeed, the
ApplePI/EI bus has timing adjustments on a per-pin basis. Making channels
wider makes no sense.

....

Fwiw, the two memory "channels" (DDR2/266-400) on the Lindenhurst family of
MCH chips (P4 and P4 Xeon) are closer to a single, double-wide bus than not.
The same could be said for the various flavors of Serverworks' CMIC chip
(DDR266-400).

The same address appears on both channels simultaneously, and the data from
both "channels" is aggregated and delivered to the FSB as a cache line with
both channels contributing equally. And clocks for all dimms on both
"channels" originate from the same source...

/daytripper ()