256-bit memory paths why not CPU's?

If Nvidia&ATI can create video cards w/256-bit paths to DDR memory why can't
Intel and/or AMD create even a 128-bit path to main memory? Even though the
Nforce2 has dual-channel DDR (which I presume is 128-bit) the Athlons only have
a 64-bit data bus.
The new 64-bit Athlons/opterons don't have a 128-bit path to memory do they?
-Bill (remove "botizer" to reply via email)

Wblane wrote:

If Nvidia&ATI can create video cards w/256-bit paths to DDR memory why
can't Intel and/or AMD create even a 128-bit path to main memory? Even
though the Nforce2 has dual-channel DDR (which I presume is 128-bit) the
Athlons only have a 64-bit data bus.
The new 64-bit Athlons/opterons don't have a 128-bit path to memory do
they? -Bill (remove "botizer" to reply via email)

Yes, they do.

As for Nvidia and ATI, they are making special purpose processors which do
not have to support a large existing base of code. Intel and AMD are quite
capable of making a chip with a 256 bit or a 2560 bit path to memory if
they want to, but making such a chip that will run Windows is another
story.

--
--John
Reply to jclarke at ae tee tee global dot net
(was jclarke at eye bee em dot net)

The Athlon 64 series has a 64-bit memory data bus, while the Athlon FX and
Opteron series feature a 128-bit bus. Hope this helps....

www.amd.com


Rich S.

"Wblane" wrote in message
...
If Nvidia&ATI can create video cards w/256-bit paths to DDR memory why
can't
Intel and/or AMD create even a 128-bit path to main memory? Even though
the
Nforce2 has dual-channel DDR (which I presume is 128-bit) the Athlons only
have
a 64-bit data bus.
The new 64-bit Athlons/opterons don't have a 128-bit path to memory do
they?
-Bill (remove "botizer" to reply via email)

"J. Clarke" wrote in message
...
Wblane wrote:

If Nvidia&ATI can create video cards w/256-bit paths to DDR memory why
can't Intel and/or AMD create even a 128-bit path to main memory? Even
though the Nforce2 has dual-channel DDR (which I presume is 128-bit) the
Athlons only have a 64-bit data bus.
The new 64-bit Athlons/opterons don't have a 128-bit path to memory do
they? -Bill (remove "botizer" to reply via email)

Yes, they do.

As for Nvidia and ATI, they are making special purpose processors which do
not have to support a large existing base of code. Intel and AMD are
quite
capable of making a chip with a 256 bit or a 2560 bit path to memory if
they want to, but making such a chip that will run Windows is another
story.

--
--John
Reply to jclarke at ae tee tee global dot net
(was jclarke at eye bee em dot net)

Its not a question of if Windows can run it or not (we're not talking about
a 64-bit/256-bit operating system here). Its a question of price. You can
make a 256-bit path to memory on the motherboard via the CPU. But its very
complicated. Too complicated at this point in time to justify the price.

Sean wrote:


"J. Clarke" wrote in message
...
Wblane wrote:

If Nvidia&ATI can create video cards w/256-bit paths to DDR memory why
can't Intel and/or AMD create even a 128-bit path to main memory? Even
though the Nforce2 has dual-channel DDR (which I presume is 128-bit)
the Athlons only have a 64-bit data bus.
The new 64-bit Athlons/opterons don't have a 128-bit path to memory do
they? -Bill (remove "botizer" to reply via email)

Yes, they do.

As for Nvidia and ATI, they are making special purpose processors which
do
not have to support a large existing base of code. Intel and AMD are
quite
capable of making a chip with a 256 bit or a 2560 bit path to memory if
they want to, but making such a chip that will run Windows is another
story.

--
--John
Reply to jclarke at ae tee tee global dot net
(was jclarke at eye bee em dot net)

Its not a question of if Windows can run it or not (we're not talking
about
a 64-bit/256-bit operating system here). Its a question of price. You
can
make a 256-bit path to memory on the motherboard via the CPU. But its
very
complicated. Too complicated at this point in time to justify the price.

OK, you're running a 32 bit program and you have a processor that can access
memory 256 bits at a time. What does it do with the 224 bits that it's not
using other than store it in the cache? Will pulling the next 8
instructions or next 8 words of memory into cache every time you do a read
improve performance significantly over pulling the next 4?

--
--John
Reply to jclarke at ae tee tee global dot net
(was jclarke at eye bee em dot net)

It's about time too! I was reading Infoworld and a writer was editorializing on
how the Apple G4 (or is it G5?) is the fastest PC system in the world. It's
interesting how he compared it only to the P4 extreme edition 3.06 and ignored
the AMD 64-bit processors completely when he came to his decision.

The Athlon 64 series has a 64-bit memory data bus, while the Athlon FX and
Opteron series feature a 128-bit bus. Hope this helps....

www.amd.com


-Bill (remove "botizer" to reply via email)

Exactly, the OS doesn't know or care how much data is clocked in -- it's
transparent. That's why the Nforce2 boards can support a 128-bit dual channel
interface to memory.


Its not a question of if Windows can run it or not (we're not talking about
a 64-bit/256-bit operating system here). Its a question of price. You can
make a 256-bit path to memory on the motherboard via the CPU. But its very
complicated. Too complicated at this point in time to justify the price.




-Bill (remove "botizer" to reply via email)

You need a refresher course in x86 architecture. Ever heard of Byte Enables?
The Byte Enables are I/O pins on Pentium class processors that "determine which
bytes must be written to external memory, or which bytes were requested by the
CPU for the current cycle. (Intel datasheet for Pentium Processors)." This is
why Pentium class processors do not have address lines A0 thru A2; the
processor always fetches 64-bits (8 bytes) at a time. The Byte Enables (B0 thru
B7) tell the CPU which of these bytes you wanted. When a cacheable read is
performed from memory, whether or not a single byte or word or double-word is
being read, a full cacheline (four doublewords, at least on the 486) of data is
read from memory. This is because the overhead of reading three more
doublewords is insignificant in comparison to fetching the first doubleword.
The principle of localization also comes into play here. Chances are that your
code/data is contiguous so why not read what you will probably be needing in
the future now. The OS doesn't care about the data bus width, otherwise you
wouldn't be able to run 95,98,ME on 386's, 486's, Pentiums, Pentium II's etc.

Here's a question for you since the original Pentium had a 64-bit data bus is
it a 64-bit processor? Since the original 80486 has 8, 80-bit registers in its
FPU is the 486 an 80-bit CPU?

OK, you're running a 32 bit program and you have a processor that can access
memory 256 bits at a time. What does it do with the 224 bits that it's not
using other than store it in the cache? Will pulling the next 8
instructions or next 8 words of memory into cache every time you do a read
improve performance significantly over pulling the next 4?

--
--John
Reply to jclarke at ae tee tee global dot net
(was jclarke at eye bee em dot net)



-Bill (remove "botizer" to reply via email)

Wblane wrote:

You need a refresher course in x86 architecture. Ever heard of Byte
Enables? The Byte Enables are I/O pins on Pentium class processors that
"determine which bytes must be written to external memory, or which bytes
were requested by the CPU for the current cycle. (Intel datasheet for
Pentium Processors)." This is why Pentium class processors do not have
address lines A0 thru A2; the processor always fetches 64-bits (8 bytes)
at a time. The Byte Enables (B0 thru B7) tell the CPU which of these bytes
you wanted. When a cacheable read is performed from memory, whether or not
a single byte or word or double-word is being read, a full cacheline (four
doublewords, at least on the 486) of data is read from memory. This is
because the overhead of reading three more doublewords is insignificant in
comparison to fetching the first doubleword. The principle of localization
also comes into play here. Chances are that your code/data is contiguous
so why not read what you will probably be needing in the future now. The
OS doesn't care about the data bus width, otherwise you wouldn't be able
to run 95,98,ME on 386's, 486's, Pentiums, Pentium II's etc.

Here's a question for you since the original Pentium had a 64-bit data bus
is it a 64-bit processor? Since the original 80486 has 8, 80-bit registers
in its FPU is the 486 an 80-bit CPU?

Here's a question for you--what will be the percentage peformance
improvement? That's the issue, not minutiae of the history of the Pentium
processor.

OK, you're running a 32 bit program and you have a processor that can
access
memory 256 bits at a time. What does it do with the 224 bits that it's
not
using other than store it in the cache? Will pulling the next 8
instructions or next 8 words of memory into cache every time you do a read
improve performance significantly over pulling the next 4?

--
--John
Reply to jclarke at ae tee tee global dot net
(was jclarke at eye bee em dot net)



-Bill (remove "botizer" to reply via email)

--
--John
Reply to jclarke at ae tee tee global dot net
(was jclarke at eye bee em dot net)

You're right that's really what it all comes down to. When the Pentiums
went to a 64-bit data bus (which all 32-bit x86 compatible processors still
use) the Pentium 75 was neck-and-neck w/the Cyrix 5x86 at 120Mhz (which had
most, if not all of the features of the early Pentiums, except a weak FPU). It
was a similar story when the 286 doubled the data bus size of the 8088. It
should make a noticeable difference.

Here's a question for you--what will be the percentage peformance
improvement? That's the issue, not minutiae of the history of the Pentium
processor.



-Bill (remove "botizer" to reply via email)