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#11
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Chas. wrote: I found some info on Amperage requirements for VRMs for the various PPro 200 CPUs. It may not be completely acurate but its a start. Some one from Tyan reported that the 1Mb PPro draws 2.5 more amps than the 256/512K PPros, and would require a higher capacity VRM. 256K should work with 11.2 Amp VRMs 512k should work with 12.4 Amp VRMs 1 MB should work with 15.5 Amp VRMs Some VRM Specs for PPro CPUs VXI VRM 073-20674-07 11.2amp VXI VRM 073-20713-01 12.4amp 5VIN VXI VRM 073-20714-01 ? VXI VRM 073-20715-01 14.5amp 5/12VIN 1.8/3.5VOUT VXI VRM 073-20674-07X 12.4amp VXI VRM 073-20740-01 16.0amp Raytheon RCB001 12.4amp Raytheon RCB006 15.5amp Canary 225529-001 ? Corsair SPX560KM ? The onboard voltage regulator on your board may not be able to support the 1MB PPros. Chas. Great info, I actually have no idea what capacity my VRMs are- I suspect they're the RCB001's, though, so I'll have to get that straightened out. I do know Tyan said the board could be used with the 1mb chips, but that's obviously dependent on the proper hardware. Thanks for that post. J. -- Pull the '-m*ps' for mail. |
#12
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"NuT CrAcKeR" wrote in message ...
the more cache will make it feel more snappy, and help most applications to some degree. However, if you really want to get jiggy with this, try to locate the PII-OD chips. 333Mhz on the 66Mhz bus, with 512K fullspeed cache. It performs like a PII-450 (in my opinon), and works in most systems that are dual compatable. I upgraded my ALR Evolution Dual 6 workstation (my webserver), and its fine. It serves up the sites i need like a bat outta hell, and I put an ALR 3drive Raid cage in there, and an Ultra SCSI Array controller (40MB/s) with 32M cache... Its a screamer, and will be for sale soon... NuTs snip I put in the second CPU tonight. Installed the VRM, changed the "undocumented" jumper and booted it up. Started right up but didn't detect the 2nd CPU. Rebooted and bingo, "Second CPU Initialized". It's a Hemi 6 Pack! The heatsink that came with the CPU had a bad fan. I pulled a big one off of an old Athlon Slot A heatsink and fixed the problem. I also put in an extra 64MB of memory for 224MB total. I found 512MB for a good price on Ebay and I also picked up 2 matched PPro 200 512k CPUs for $12! This motherboard uses 1 onboard voltage regulator and 1 VRM. The onboard VR probably can't take the current draw of a PPro 200 1Mb CPU. Chas. |
#13
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J Rennert wrote in message ...
Chas. wrote: Do the PPro 200s with 512k or 1M cache offer much in the way of performance advantage over the 256k CPUs. Please no comments about getting a more modern system. I have PCs all over the house. This is sort of like rebuilding an old car. Chas. Heh, I know what you mean- I searched long and hard for a dual Tyan PPro board and some 1mb chips, then found eight 128mb SIMMs to stuff in there to max it out. Haven't found time to get it going yet, but it'll run gentoo for sure. The P6 was/is an underrated chip. I believe it's generally accepted that you feed webservers clock speed and DB servers cache. All relative to the age of your chip, anyway. Good luck with the project, it sounds like fun. Make sure and check to see if you need an additional VRM- those can sometimes cost more than the old CPU. J. I put in the second CPU tonight. Installed the VRM, changed the "undocumented" jumper and booted it up. Started right up but didn't detect the 2nd CPU. Rebooted and bingo, "Second CPU Initialized". It's a Hemi 6 Pack! The heatsink that came with the CPU had a bad fan. I pulled a big one off of an old Athlon Slot A heatsink and fixed the problem. I also put in an extra 64MB of memory for 224MB total. I found 512MB for a good price on Ebay and I also picked up 2 matched PPro 200 512k CPUs for $12! This motherboard uses 1 onboard voltage regulator and 1 VRM. The onboard VR probably can't take the current draw of a PPro 200 1Mb CPU. Chas. |
#14
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"Chas" == Chas writes:
Chas I put in the second CPU tonight. Installed the VRM, changed the Chas "undocumented" jumper and booted it up. Started right up but Chas didn't detect the 2nd CPU. Rebooted and bingo, "Second CPU Chas Initialized". What is this undocumented jumper? I never changed any jumper when adding a CPU, and it worked fine for me. Did I miss something all these years? Let me know Thanks |
#15
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"Chas" == Chas writes:
Chas Spam Me Please wrote in message Chas ... "Chas" == Chas writes: Chas I put in the second CPU tonight. Installed the VRM, changed the Chas "undocumented" jumper and booted it up. Started right up but Chas didn't detect the 2nd CPU. Rebooted and bingo, "Second CPU Chas Initialized". What is this undocumented jumper? I never changed any jumper when adding a CPU, and it worked fine for me. Did I miss something all these years? Let me know Thanks Chas Hmmm, I guess you're right. There is a W10 jumper next to the Chas top CPU socket on Micronics W6-LI mobos. I read somewhere in an Chas NG message that this jumper needs to be moved from 1-2 to 2-3 Chas for dual processors. It turns out that the jumper controls Chas pipelined bus cycles... whatever that is. It's function isn't Chas described in the less than useless Micron manual. The Micronics Chas motherboard manual is a little better. Okay - is it faster with this jumper enabled? Anyone has done any benchmarks? Thanks for the info |
#16
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Okay - is it faster with this jumper enabled? Anyone has done any
benchmarks? Why do they always speak of "faster"? Are stability and determinability not positive values? On the other hand, they do not deserve it better. -- ------- http://grassomusic.de ------- |
#17
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"Grasso" == Grasso writes:
Okay - is it faster with this jumper enabled? Anyone has done any benchmarks? Grasso Why do they always speak of "faster"? Are stability and Grasso determinability not positive values? On the other hand, they Grasso do not deserve it better. Just curious. Those are great questions also. Does anyone have the answer for any of the above questions? Thanks |
#18
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On Wed, 13 Aug 2003 00:52:59 -0500, Spam Me Please wrote:
"Grasso" == Grasso writes: Okay - is it faster with this jumper enabled? Anyone has done any benchmarks? Grasso Why do they always speak of "faster"? Are stability and Grasso determinability not positive values? On the other hand, they Grasso do not deserve it better. Just curious. Those are great questions also. Does anyone have the answer for any of the above questions? Here's an animation, with 4 CPUs of the PPro GTL+ Bus and memory bus signalling showing memory transactions: http://www.warthman.com/ex-ppro.htm... URL originally supplied by Dave Wang IIRC. Does your system work "properly" in dual mode with the jumper in either position? I haven't looked at the details of CPU strapping but I'm wondering if the jumper might be to allow for strapping the CPU to eliminate the overhead of bus arbitration in single CPU mode - note the BREQn# signals. Hmmm, not sure what would happen if it was strapped wrongly for dual mode. The other possibility would be setting the size of the IOQ - Chas mentioned something about it possibly having something to do with pipelining of addresses. Maybe some tests with Stream would show up any differences. Rgds, George Macdonald "Just because they're paranoid doesn't mean you're not psychotic" - Who, me?? |
#19
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(George Macdonald) wrote in message ...
On Wed, 13 Aug 2003 00:52:59 -0500, Spam Me Please wrote: "Grasso" == Grasso writes: Okay - is it faster with this jumper enabled? Anyone has done any benchmarks? Grasso Why do they always speak of "faster"? Are stability and Grasso determinability not positive values? On the other hand, they Grasso do not deserve it better. Just curious. Those are great questions also. Does anyone have the answer for any of the above questions? Here's an animation, with 4 CPUs of the PPro GTL+ Bus and memory bus signalling showing memory transactions: http://www.warthman.com/ex-ppro.htm... URL originally supplied by Dave Wang IIRC. Does your system work "properly" in dual mode with the jumper in either position? I haven't looked at the details of CPU strapping but I'm wondering if the jumper might be to allow for strapping the CPU to eliminate the overhead of bus arbitration in single CPU mode - note the BREQn# signals. Hmmm, not sure what would happen if it was strapped wrongly for dual mode. The other possibility would be setting the size of the IOQ - Chas mentioned something about it possibly having something to do with pipelining of addresses. Maybe some tests with Stream would show up any differences. Rgds, George Macdonald George, Here's the info from the Micronics Manual: Jumper settings for the Host Bus Agents pipelining mode. Host Bus Agents are devices connected to the CPU local bus which include the CPUs and the 440FX chipset. Host Bus Agents can generate, up to eight at a time, multiple overlapped (or Pipelined) transactions ( or Bus Cycles). W10 Jumper Settings - Pipelining Mode Settings Normal (Default) - Open Reserved - Closed Chas. |
#20
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