Which atrributes are critical when matching PCxx00 DDR memory?

I noticed that some memory modules are 2.6V CL3, while others are 2.5V
CL2.5. Certain maximums such as row/refresh active times can be
different as well.

Assuming one matches a new PC2700 or PC3200 with existing PC2700 or
PC3200, are there specs that absolutely must match?

In article , Patrick Coghlan
wrote:

I noticed that some memory modules are 2.6V CL3, while others are 2.5V
CL2.5. Certain maximums such as row/refresh active times can be
different as well.

Assuming one matches a new PC2700 or PC3200 with existing PC2700 or
PC3200, are there specs that absolutely must match?

On a single channel chipset, there is no matching requirement as
such. The BIOS is supposed to look at all modules, then select
a set of timings suitable for running the slowest of the modules.
You should be able to mix brands, as JEDEC defines common electrical
parameters, to try to make memory chips interchangable, as much
as possible. (Like specifying minimum capacitance, when minimizing
capacitance might have enhanced performance.)

On a dual channel chipset, the purpose of the matching requirement,
is to allow the sticks in each channel, to be run with the same
timing, such that the data becomes available at the same point
in time. Since the chipset designers have various address interleave
options available to them (interleaving, like storing words 0,4,8,12
at addresses 0, 1024, 2048, 3072), that imposes a further requirement
on the internal addressing of blocks of memory. If no interleave
options are used, and a pure linear mapping is at work, in fact
there is no need to do anything more than is done for a single
channel system. (An example of an unconstrained dual channel
chipset is Nforce2, where you can put any DIMMs you want in there,
and they'll run dual channel for whatever amount of RAM matches
in quantity on each channel.)

Inside a memory chip, are rows, columns, and banks. There is
an access procedure for a bank and a page of memory, with an
overhead sequence of cycles to accomplish it. The page can
be left open by a first operation, and if the memory controller
keeps track of what it is doing, it can do a second operation
on an already "open" page. Now, if you have two DIMMs, one
sitting on each memory channel, and you allowed the
row x column x bank attributes to be different on the two
DIMMs, there would be a need to track page opening and closing,
and the DIMMs would fall out of step with one another.

The fourth dimension is ranks. A DIMM can be single or double
sided, and the term single rank or dual rank is used, to avoid
confusion with the term bank, which is already being used to
refer to the four banks inside a memory chip. A rank is enough
chips to make a 64 bit wide array, so (8) x8 chips or (4) x16
chips on the side of a DIMM, is enough.

To match DIMMs, such that there is fair flexibility in selecting
address interleave patterns, this leads to a need to match
rows, columns, banks, and ranks, on the DIMMs sitting across
from one another on the two channels. That is sufficient matching
for the majority of chipsets used on Intel boards.

The observed behavior on Athlon64 systems seems to be a little
different, and the BIOS is looking for more fields to match,
than theory can justify. I only mention this, to explain why some
people have a hard time with their Athlon64 systems. It seems
to be a BIOS issue.

As for the voltage requirement, generally all DIMMs will be
running with the same power source. All memory chips have the
same practical supply voltage range. DDR400 memory was added as
a separate operating point, to the JEDEC spec, and at the time,
the memory makers determined that to get better yielding parts,
operation at 2.6V would make that possible, rather than the
2.5V which was adequate at DDR333 or slower rates. Practical
DIMMs can be run up to maybe 2.8V or so, without consequences.
Above that voltage, there are differences in the use of internal
voltage regulators on the silicon die, and some implementations
get hotter than others, due to the dumping of excess voltage
when operated at higher voltages. Thus some DIMMs will fry
overnight, if run at 3.0V, while others have apparently run
for years at 3.2V. A setting in the BIOS, of 2.7 or 2.8V will
frequently stabilize memory that is really out of its league.

On refresh timing (like 15.625uS), there are differences as
the density of the chip goes up. Most people leave that setting
at Auto.

As for the four timing parameters, measured in clock ticks,
you will see some DIMMs with 3-3-3-8 timing. I believe that
would be considered to be the JEDEC standard timing, what
each manufacturer agreed to in the JEDEC standards meeting.
There are plenty of "performance" memory products, with
timings that are tighter than that, such as 2-2-2-5 timing.
In many cases, the SPD on the DIMM of these performance modules
may contain a slightly looser set of numbers, requiring the
user to set the final rated value manually. So, once you
get into performance modules, things get a bit more interesting
from a customer perspective.

So, to summarize, what do you need to know, for DDR selection ?

1) For operation at DDR400 (200MHz memory clock), use a minimum
of 2.6V for memory stability, and up to 2.8V for some brands
that explicitly state a need for it. Use only as much voltage
as is needed to pass Prime95 error free. (Many motherboards
which don't have voltage settings, are already using elevated
voltages levels anyway, so no need to panic. There is only
the odd server motherboard design that is hobbled with a
fixed 2.5V source.)
2) Single channel systems don't have matching requirements. A
DIMM rated for PC3200, can operate at DDR400, DDR333, DDR266,
DDR200 (and by spec, even a bit slower than that). Thus, a
higher rated DIMM, can operate at lower rates, when needed,
to match some slower DIMM, like a PC2100 one. The BIOS will
locate the slowest DIMM, and set channel timing to those
slowest parameters. (Some chipset lack flexibility in the
relationship of memory bus to FSB, and slowing the memory
operation, causes the FSB and the processor core speed to
drop as well. Such computers give the user an incentive to
use proper speed rated memory, so the processor runs at
normal speeds.)
3) The majority of dual channel systems, need the dimensions of
rows, columns, banks, and ranks to match. A double sided
512MB DIMM uses (16) 32Mx8 chips. A single sided 512MB DIMM
uses (8) 64Mx8 chips. The four dimensional parameters on
these two products don't match, so the chipset will revert
to single channel operation. But it will still work and
it will still compute. It is just the maximum memory
bandwidth will be reduced. Certain address interleaving
patterns could not be used with the two above mentioned
DIMMs, and address interleave gives a slight improvement
in bandwidth.
4) The memory timing parameters, whether they are 3-3-3-8,
2.5-3-3-8, or 2-2-2-5, are all a matter of user perception.
The BIOS will pick the slowest set of timings, of all the
sticks. Enhanced timing does buy a bit more memory performance,
but is seldom cost effective (double memory price, 5% more
application performance).

To learn more about the contents of the SPD chip on the DIMM,
have a look at this spec:

http://web.archive.org/web/200304170..._02_04R11A.PDF

For a primer on memory, try this corsairmicro slide show:

http://corsairmicro.com/corsair/prod...707/index.html

Oh, one other parameter I forgot, is command rate, which is
either 1T or 2T. This is not a factor of the memory module
itself, but is a compensation for memory address bus loading.
All the memory chips sit in parallel on the address bus on the
channel. The more modules, the higher the capacitance, and the
longer it takes for the final value of the address to settle.

If there is only one DIMM on the channel, the address is presented
for one clock cycle, and is sampled by the module at the end of
the cycle. The clock period is 5ns at DDR400, and the data valid
window is a small fraction of that, near the rising clock edge.
If the BIOS determines that the potential loading is going to be
too much for the memory controller, the memory controller is
configured to present the address for two cycles, A qualifying
signal, that says "sample now", is set to tell the memory to
sample the data at the end of the second cycle. This corresponds
to the Command Rate 2T setting. On Intel boards, this parameter
can be hidden from the user and from the BIOS designer, so there
is no way to know what is happening. On some AMD systems, this
is exposed, and is controllable by the user. On Athlon64 systems,
this leads to the operating choices of DDR333 1T or DDR400 2T
when using four DIMMs. Command Rate 2T operating mode saps
up to 20% memory bandwidth, but this is only 6% application
performance or so. And you do see the improvement of 400/333
which is 20% improvement. In fact, the DDR400 2T setting
has the better performance, but you'll find much whining from
AMD users on this issue. If a memory advertise "1T operation",
I don't see much meaning in the claim, as it is a memory
controller operations issue, rather than a DIMM parameter.

I didn't get into the three practical memory types:

1) Unbuffered with no ECC. (64 bit wide memory array)
2) Unbuffered with ECC (72 bit wide memory array)
2) Registered with ECC (72 bit wide memory array)

Registered memory adds an additional cycle of delay to the
address/command bus. A register chip on the module isolates
the address bus loading of the module, from the memory bus.
Registered memory is usually limited to server boards, where
the memory channel has more DIMMs on it than on a desktop board.
The server user accepts a bandwidth drop, for the opportunity to
have a larger quantity of memory.

ECC is error checking and correcting, which is a nice enhancement
if you seek extra protection against memory errors. Not all
desktop boards support the option, but a module with the
extra chip for ECC could still in principle, be used on such
a board. (As long as the BIOS handles it without complaining.)
If you wish to use ECC, all modules should be ECC type, to
get proper coverage.

HTH,
Paul

In a nutshell, then, the user must (or at least, should) ensure that the
dimensions are the same and the BIOS will compensate for any memory
timing differences.

Thanks for the detailed response!

-Pat

Paul wrote:

In article , Patrick Coghlan
wrote:



I noticed that some memory modules are 2.6V CL3, while others are 2.5V
CL2.5. Certain maximums such as row/refresh active times can be
different as well.

Assuming one matches a new PC2700 or PC3200 with existing PC2700 or
PC3200, are there specs that absolutely must match?



On a single channel chipset, there is no matching requirement as
such. The BIOS is supposed to look at all modules, then select
a set of timings suitable for running the slowest of the modules.
You should be able to mix brands, as JEDEC defines common electrical
parameters, to try to make memory chips interchangable, as much
as possible. (Like specifying minimum capacitance, when minimizing
capacitance might have enhanced performance.)

On a dual channel chipset, the purpose of the matching requirement,
is to allow the sticks in each channel, to be run with the same
timing, such that the data becomes available at the same point
in time. Since the chipset designers have various address interleave
options available to them (interleaving, like storing words 0,4,8,12
at addresses 0, 1024, 2048, 3072), that imposes a further requirement
on the internal addressing of blocks of memory. If no interleave
options are used, and a pure linear mapping is at work, in fact
there is no need to do anything more than is done for a single
channel system. (An example of an unconstrained dual channel
chipset is Nforce2, where you can put any DIMMs you want in there,
and they'll run dual channel for whatever amount of RAM matches
in quantity on each channel.)

Inside a memory chip, are rows, columns, and banks. There is
an access procedure for a bank and a page of memory, with an
overhead sequence of cycles to accomplish it. The page can
be left open by a first operation, and if the memory controller
keeps track of what it is doing, it can do a second operation
on an already "open" page. Now, if you have two DIMMs, one
sitting on each memory channel, and you allowed the
row x column x bank attributes to be different on the two
DIMMs, there would be a need to track page opening and closing,
and the DIMMs would fall out of step with one another.

The fourth dimension is ranks. A DIMM can be single or double
sided, and the term single rank or dual rank is used, to avoid
confusion with the term bank, which is already being used to
refer to the four banks inside a memory chip. A rank is enough
chips to make a 64 bit wide array, so (8) x8 chips or (4) x16
chips on the side of a DIMM, is enough.

To match DIMMs, such that there is fair flexibility in selecting
address interleave patterns, this leads to a need to match
rows, columns, banks, and ranks, on the DIMMs sitting across
from one another on the two channels. That is sufficient matching
for the majority of chipsets used on Intel boards.

The observed behavior on Athlon64 systems seems to be a little
different, and the BIOS is looking for more fields to match,
than theory can justify. I only mention this, to explain why some
people have a hard time with their Athlon64 systems. It seems
to be a BIOS issue.

As for the voltage requirement, generally all DIMMs will be
running with the same power source. All memory chips have the
same practical supply voltage range. DDR400 memory was added as
a separate operating point, to the JEDEC spec, and at the time,
the memory makers determined that to get better yielding parts,
operation at 2.6V would make that possible, rather than the
2.5V which was adequate at DDR333 or slower rates. Practical
DIMMs can be run up to maybe 2.8V or so, without consequences.
Above that voltage, there are differences in the use of internal
voltage regulators on the silicon die, and some implementations
get hotter than others, due to the dumping of excess voltage
when operated at higher voltages. Thus some DIMMs will fry
overnight, if run at 3.0V, while others have apparently run
for years at 3.2V. A setting in the BIOS, of 2.7 or 2.8V will
frequently stabilize memory that is really out of its league.

On refresh timing (like 15.625uS), there are differences as
the density of the chip goes up. Most people leave that setting
at Auto.

As for the four timing parameters, measured in clock ticks,
you will see some DIMMs with 3-3-3-8 timing. I believe that
would be considered to be the JEDEC standard timing, what
each manufacturer agreed to in the JEDEC standards meeting.
There are plenty of "performance" memory products, with
timings that are tighter than that, such as 2-2-2-5 timing.
In many cases, the SPD on the DIMM of these performance modules
may contain a slightly looser set of numbers, requiring the
user to set the final rated value manually. So, once you
get into performance modules, things get a bit more interesting
from a customer perspective.

So, to summarize, what do you need to know, for DDR selection ?

1) For operation at DDR400 (200MHz memory clock), use a minimum
of 2.6V for memory stability, and up to 2.8V for some brands
that explicitly state a need for it. Use only as much voltage
as is needed to pass Prime95 error free. (Many motherboards
which don't have voltage settings, are already using elevated
voltages levels anyway, so no need to panic. There is only
the odd server motherboard design that is hobbled with a
fixed 2.5V source.)
2) Single channel systems don't have matching requirements. A
DIMM rated for PC3200, can operate at DDR400, DDR333, DDR266,
DDR200 (and by spec, even a bit slower than that). Thus, a
higher rated DIMM, can operate at lower rates, when needed,
to match some slower DIMM, like a PC2100 one. The BIOS will
locate the slowest DIMM, and set channel timing to those
slowest parameters. (Some chipset lack flexibility in the
relationship of memory bus to FSB, and slowing the memory
operation, causes the FSB and the processor core speed to
drop as well. Such computers give the user an incentive to
use proper speed rated memory, so the processor runs at
normal speeds.)
3) The majority of dual channel systems, need the dimensions of
rows, columns, banks, and ranks to match. A double sided
512MB DIMM uses (16) 32Mx8 chips. A single sided 512MB DIMM
uses (8) 64Mx8 chips. The four dimensional parameters on
these two products don't match, so the chipset will revert
to single channel operation. But it will still work and
it will still compute. It is just the maximum memory
bandwidth will be reduced. Certain address interleaving
patterns could not be used with the two above mentioned
DIMMs, and address interleave gives a slight improvement
in bandwidth.
4) The memory timing parameters, whether they are 3-3-3-8,
2.5-3-3-8, or 2-2-2-5, are all a matter of user perception.
The BIOS will pick the slowest set of timings, of all the
sticks. Enhanced timing does buy a bit more memory performance,
but is seldom cost effective (double memory price, 5% more
application performance).

To learn more about the contents of the SPD chip on the DIMM,
have a look at this spec:

http://web.archive.org/web/200304170..._02_04R11A.PDF

For a primer on memory, try this corsairmicro slide show:

http://corsairmicro.com/corsair/prod...707/index.html

Oh, one other parameter I forgot, is command rate, which is
either 1T or 2T. This is not a factor of the memory module
itself, but is a compensation for memory address bus loading.
All the memory chips sit in parallel on the address bus on the
channel. The more modules, the higher the capacitance, and the
longer it takes for the final value of the address to settle.

If there is only one DIMM on the channel, the address is presented
for one clock cycle, and is sampled by the module at the end of
the cycle. The clock period is 5ns at DDR400, and the data valid
window is a small fraction of that, near the rising clock edge.
If the BIOS determines that the potential loading is going to be
too much for the memory controller, the memory controller is
configured to present the address for two cycles, A qualifying
signal, that says "sample now", is set to tell the memory to
sample the data at the end of the second cycle. This corresponds
to the Command Rate 2T setting. On Intel boards, this parameter
can be hidden from the user and from the BIOS designer, so there
is no way to know what is happening. On some AMD systems, this
is exposed, and is controllable by the user. On Athlon64 systems,
this leads to the operating choices of DDR333 1T or DDR400 2T
when using four DIMMs. Command Rate 2T operating mode saps
up to 20% memory bandwidth, but this is only 6% application
performance or so. And you do see the improvement of 400/333
which is 20% improvement. In fact, the DDR400 2T setting
has the better performance, but you'll find much whining from
AMD users on this issue. If a memory advertise "1T operation",
I don't see much meaning in the claim, as it is a memory
controller operations issue, rather than a DIMM parameter.

I didn't get into the three practical memory types:

1) Unbuffered with no ECC. (64 bit wide memory array)
2) Unbuffered with ECC (72 bit wide memory array)
2) Registered with ECC (72 bit wide memory array)

Registered memory adds an additional cycle of delay to the
address/command bus. A register chip on the module isolates
the address bus loading of the module, from the memory bus.
Registered memory is usually limited to server boards, where
the memory channel has more DIMMs on it than on a desktop board.
The server user accepts a bandwidth drop, for the opportunity to
have a larger quantity of memory.

ECC is error checking and correcting, which is a nice enhancement
if you seek extra protection against memory errors. Not all
desktop boards support the option, but a module with the
extra chip for ECC could still in principle, be used on such
a board. (As long as the BIOS handles it without complaining.)
If you wish to use ECC, all modules should be ECC type, to
get proper coverage.

HTH,
Paul