RAM Latency Confusion

I wrote a program to measure the "end to end" latency
for reading a random 32-bit word in RAM. Basically,
it works like this:

1. It creates a circular list of pointers in memory in
which each pointer points at random to another
pointer in the list. The list occupies 256MB of
memory.

2. Then, by iterating through the list, the program
computes the time required to execute the
instruction, "mov edi, [edi]". When I run the
program, the time I'm getting is about 230
nanoseconds, which, on my computer translates
to 23 CPU cycles.

My computer has an MSI 694T Pro mainboard, a
1GHz PIII Celeron CPU, 100MHz FSB, and 512MB
PC133 CL2 ECC RAM set to run at 133MHz.
According to SiSoft Sandra, its performance is right in
line with similar configurations.

I have the RAM set to "turbo" in the BIOS, which I
believe sets the RAM timings to 2-1-1-1, which would
mean that it should take 5 cycles to read in a (32 byte)
cache line. (Each random access as described above
would pull in a cache line.)

Why am I measuring 23 cycles? What part of "RAM
latency" don't I understand??

-- Bob Day

On Sat, 27 Sep 2003 20:51:20 GMT, "Bob Day"
wrote or quoted :

Why am I measuring 23 cycles? What part of "RAM
latency" don't I understand??

One thing you want to do is cycle the ram at least once before you
start timing to make sure there is no virtual ram paging overhead or
allocation overhead.

--
Canadian Mind Products, Roedy Green.
Coaching, problem solving, economical contract programming.
See http://mindprod.com/jgloss/jgloss.html for The Java Glossary.

"Roedy Green" wrote in message
...
On Sat, 27 Sep 2003 20:51:20 GMT, "Bob Day"
wrote or quoted :

Why am I measuring 23 cycles? What part of "RAM
latency" don't I understand??

One thing you want to do is cycle the ram at least once before you
start timing to make sure there is no virtual ram paging overhead or
allocation overhead.

Thanks, Roedy. I put in a loop to iterate through the
random pointer list 100,000 times before starting the
timing. It didn't lower the number of cycles I'm measuring
to access a random location by much (it's now an average
of 22.5), but it did make the measurements significantly
more consistent from run to run (I'm getting numbers like
22.528, 22.535, and 22.522). But still, I don't understand
why it's not around 5 cycles plus maybe a few cycles for
the mov instruction itself.

-- Bob Day

Question: What is SPD?
Answer: SPD (Serial Presence Detect) is a new feature available on SDRAM
DIMMs. This feature is an attempt to solve industry-wide compatibility
problems by making it easier for the BIOS to properly configure the system
to optimize SDRAM performance profiles. The SPD device is an 8-pin serial
EEPROM chip that stores information on the DIMM modules' size, speed,
voltage, drive strength, and number of row and column addresses. When the
BIOS reads these parameters during the POST routine, it automatically
adjusts values in the BIOS Chipset section for maximum reliability and
performance
http://www.supermicro.com/TECHSUPPOR...Memory_FAQ.htm


--
Chris
Technical director CKCCOMPUSCRIPT
Apple Computers, Intel, Roland audio, ATI, Microsoft, Sun Solaris, Cisco and
Silicone Graphics.
Wholesale distributor and specialist audio visual computers and servers
FREE SUPPORT @,
http://www.ckccomp.plus.com/site/page.HTM


"Bob Day" wrote in message
...
I wrote a program to measure the "end to end" latency
for reading a random 32-bit word in RAM. Basically,
it works like this:

1. It creates a circular list of pointers in memory in
which each pointer points at random to another
pointer in the list. The list occupies 256MB of
memory.

2. Then, by iterating through the list, the program
computes the time required to execute the
instruction, "mov edi, [edi]". When I run the
program, the time I'm getting is about 230
nanoseconds, which, on my computer translates
to 23 CPU cycles.

My computer has an MSI 694T Pro mainboard, a
1GHz PIII Celeron CPU, 100MHz FSB, and 512MB
PC133 CL2 ECC RAM set to run at 133MHz.
According to SiSoft Sandra, its performance is right in
line with similar configurations.

I have the RAM set to "turbo" in the BIOS, which I
believe sets the RAM timings to 2-1-1-1, which would
mean that it should take 5 cycles to read in a (32 byte)
cache line. (Each random access as described above
would pull in a cache line.)

Why am I measuring 23 cycles? What part of "RAM
latency" don't I understand??

-- Bob Day