Processor heat dissipation, Leakage current, voltages & clockspeed

"Franc Zabkar" wrote in message
...
On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd. The
only cubic dependency is for dynamic power (see my other post in this
thread). It's all very confusing ...


Franc, the cubic dependence in Intel's formulas is because
they are talking broadly about future power envelops, and
they assumed that the top frequency of a processor family is
approximately proportional to supplied voltage Vdd.
When factored with standard (Vdd)^2 dependence for dynamic
power, they have (Vdd)^3, but the frequency is excluded.

Hope this clears the cubic issue.

Regards,

- aap

On Mon, 01 Nov 2004 06:19:21 +1100, Franc Zabkar wrote:

On Sat, 30 Oct 2004 22:04:04 -0400, keith put finger
to keyboard and composed:

On Sat, 30 Oct 2004 06:12:09 +1000, Franc Zabkar wrote:

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd.

Leakage current, particularly gate tunneling, goes up by at *least* the
square of the voltage, this power goes as the cube. Sub-threshold current
is a similar issue. Think about the power dissipated in a diode, as it's
forward bias increase. Leakage is worse.

The tutorial that was alluded to by the OP distinguishes between
static power and leakage power. All other references appear to equate
the two concepts, as you have done. I would think that in the "static"
state as many as half the transistors could be ON and therefore
drawing significant current. The rest would be OFF and drawing a
comparatively negligible leakage current????

In classical CMOS curcuits, an "on" or "off" transistor dissipates *no*
power. It's only the ones switching that dissipate power (that's the
classical "dynamic" power). Add in leakage and there is no "off"
transistor. They're all dissipating power, "on" or "off".


The only cubic dependency is for dynamic power (see my other post in
this thread).

Nope. Dynamic power goes with the square of the voltage.

OK, so my statement was somewhat ambiguous. I meant that I found only
two online references that mentioned cubic dependency in relation to
power dissipation, and neither of these references talked about static
power or leakage, only dynamic power.

shrug Dynamic power is basically a charge pump, pumping power
to-and-fro capicators. These charges (thus current) are linear with
voltage, thus the power quadratic.

Leakage is far from linear. Both leakage current terms (sub-threshold
and gate tunneling) are at least quadratic, thus the power is cubic.

This is the first one:
http://www.intel.com/technology/itj/..._awareness.htm

The article discusses the Pentium M processor. It arrives at a cubic
dependency by assuming that frequency is proportional to Vcore. I
confess I don't understand the basis for this assumption.

Not what we're discussing at all. Of course if you raise the frequeny in
proportion to the voltage, the *dynamic* power will cube (P~F*V^2). This
has *nothing* to do with leakage.

This is the second article:
http://books.nap.edu/html/embedded_e...re/ch2_b3.html

It examines the effects on power dissipation in an existing design when
it is scaled to a new technology. A cubic dependency arises because
newer processes result in lower capacitances and a lower Vcore.

Try searching on *leakage* (even refine that to "sub-threshold" and
"gate tunneling") power, not dynamic power. YOu're confusing yourself
with too many variables.

Think of a
CMOS switch as a charge pump. The charge goes up linearly with the
voltage, thus the power as the square.

It's all very confusing ...

Apparently. This is new territory for many.

Well, I understand the concept of leakage from my Uni days, and I
understand how the formula for dynamic power is derived. In the latter
case the energy stored by a capacitor is 1/2 * C * V^2, and this energy
is moved twice during one clock cycle. So power = (1/2 * C * V^2) * 2f =
C * V^2 * f.

Exactly. Now forget that term in the equation. Concentrate on the V/I
charactistics of the devices. As a very simple model, think of leakage as
a diode (of indeterminate forward drop) between the rails. That "leakage"
current will go up exponentially with the voltage, thus its power by the
cube. This is independent of any dynamic power issues, like frequency.

That only leaves the concept of static power as opposed to leakage
power. I don't understand why some references distinguish between the
two, and others do not. How do these parameters differ, ie what are the
mechanisms underlying static power as opposed to leakage?

Forget your notions about "static power". As defined above (circuits
designed to draw DC current) it's a trivial matter. What is now
considered to be "static power" is all power that doesn't conform to the
P~F*V^2 *dynamic* power model. ...and *leakage* swamps that.

--
Keith