Processor heat dissipation, Leakage current, voltages & clockspeed

keith wrote:

On Mon, 25 Oct 2004 10:04:51 +0000, Johannes H Andersen wrote:



keith wrote:

On Sun, 24 Oct 2004 23:24:42 +0000, Johannes H Andersen wrote:



The little lost angel wrote:

I know I'm a bit slow to start looking up this since the Prescott
thrust the issue into lime light. I didn't quite follow the major
discussion some weeks back. My friend got himself a spanking new
Prescott and claims it wasn't that hot despite claims. Yet Intel did
cancel the 4Ghz version so it got me thinking again whether the heat
increases dramatically with clockspeed. Since leakage was the big
thing thrown about, whether that was what increased with clockspeed.
And whether we could do any experiments to test it out.

A CPU transistor is like an imperfect switch. If the switch is on or off,
no power is dissipated in the switch, but during the switching it
consumes most power when it's halfway between on and off. Hence for the
same device, the power consumption from switching is proportional to the
number of switchings in the circuit. The power can be reduced if the
switching itself can be made faster and/or the voltage/amp can be reduced.

That was more or less true five years ago, but as L'Angel is trying to
understand, this is no longer true. Deep sub-micron processes leak like
hell. ...so much so that the active power isn't the major worry going
forward.

BTW, even in your model, it's not the switch that dictates the power, but
the load (in this case capacitance).

--
Keith

Obviously, my model was simplified.

...to the point of being useless. What you said was more or less true
five years ago. It is *not* today.

A transistor is not a perfect switch,
hence it consumes power whether on or off, but maximum transistor power
is consumed during the switching halfway between on and off.

That is not true. You're only considering what L'Angel's reference
called, "short circuuit" power. By no means is this a huge deal, nor has
it ever been, with the exception of some really exotic high-power logic
(like 74ASxxx and 74Fxxx).

The faster it can switch, the less power is consumed.

Wrong. The capacitance on the load is the same, so the same charge is
transfered, thus the same power dissipated. ...all else equal.

Smaller distances makes for faster switching,

Irrelevant. All else being the same, the same charge is transfered. This
is why (for a goven processor) the active power dissipation is
proportional to the frequency.

but also apparently for higher leak currents, unless
some new structure or material can be found to keep the leaking under
control.

Deep sub-micron processes leak like sieves, yes, but that's a different
issue than what you raise above.

The increase in speed has always been dramatic and because the trend has
lasted 25 years, we expect it to continue as a matter of course.

"We"?? LOL Face the facts. *We* are fetting periously close to atomic
dimensions and the voltage gadients are constantly flirting with the MV/cm
"limit". *Wee* now have 100A on a chip, not much bigger across than the
wire supplying power to your eletric stove. ...and the current is alll on
the "surface". The power density of these things are on the order of a
*BILLION* times that of ol' Sol. Another 25 years? I'm glad I'm not
going to be the one whipped into producing that fantasy. ;-)

Ten years ago or so I was thrown into studying parallel computing; it was
said that the trend in speed surely couldn't continue. Now this field
has matured and there many really nice parallel algorithms, but the
problem it that it's a niche field; the systems were/are expensive and
manufacturer specific, not really suitable for standard software
products. I often spent more time 'parallizing' than on the problem I
wished to solve. Moreover, the resulting programs became 'solidified'
and virtually un-maintainable. Nevertheless, I learned many small habits
which might help in a pipelined environment, such as e.g. unrolling and
looping matrix multiplications the best way round.

??? Where did this change-of-subject come from?

--
Keith

That I haven't answered is no indication that I agree with you. It just
means that I've given up.

On Thu, 28 Oct 2004 18:06:37 +1000, Franc Zabkar wrote:

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

Curious... How are you going to measure the device power/current?

I suppose you could get a rough idea by monitoring the power
consumption on the AC side with a wattmeter. Of course this figure
would be influenced by the PSU's efficiency, but you could estimate
this by testing with a fixed resistive load on the +5V rail, say. For
example, if adding a 20W DC load drew an additional 25W from the
mains, then the PSU's efficiency would be 80%.

Forget the efficiency (which is not a constant). How do you shut down the
clocks to the CPU without "suspending" the rest of the system? Theidea
here is to measure the CPU, or more precisely the technology, not the
entire system. To do that the processor power has to be isolated. While
this certainly can be done, it's not something a casual user could do.

--
Keith

On Thu, 28 Oct 2004 19:34:22 +0000, Johannes H Andersen wrote:



keith wrote:

On Mon, 25 Oct 2004 10:04:51 +0000, Johannes H Andersen wrote:



keith wrote:

On Sun, 24 Oct 2004 23:24:42 +0000, Johannes H Andersen wrote:



The little lost angel wrote:

I know I'm a bit slow to start looking up this since the Prescott
thrust the issue into lime light. I didn't quite follow the major
discussion some weeks back. My friend got himself a spanking new
Prescott and claims it wasn't that hot despite claims. Yet Intel did
cancel the 4Ghz version so it got me thinking again whether the heat
increases dramatically with clockspeed. Since leakage was the big
thing thrown about, whether that was what increased with clockspeed.
And whether we could do any experiments to test it out.

A CPU transistor is like an imperfect switch. If the switch is on or off,
no power is dissipated in the switch, but during the switching it
consumes most power when it's halfway between on and off. Hence for the
same device, the power consumption from switching is proportional to the
number of switchings in the circuit. The power can be reduced if the
switching itself can be made faster and/or the voltage/amp can be reduced.

That was more or less true five years ago, but as L'Angel is trying to
understand, this is no longer true. Deep sub-micron processes leak like
hell. ...so much so that the active power isn't the major worry going
forward.

BTW, even in your model, it's not the switch that dictates the power, but
the load (in this case capacitance).

--
Keith

Obviously, my model was simplified.

...to the point of being useless. What you said was more or less true
five years ago. It is *not* today.

A transistor is not a perfect switch,
hence it consumes power whether on or off, but maximum transistor power
is consumed during the switching halfway between on and off.

That is not true. You're only considering what L'Angel's reference
called, "short circuuit" power. By no means is this a huge deal, nor has
it ever been, with the exception of some really exotic high-power logic
(like 74ASxxx and 74Fxxx).

The faster it can switch, the less power is consumed.

Wrong. The capacitance on the load is the same, so the same charge is
transfered, thus the same power dissipated. ...all else equal.

Smaller distances makes for faster switching,

Irrelevant. All else being the same, the same charge is transfered. This
is why (for a goven processor) the active power dissipation is
proportional to the frequency.

but also apparently for higher leak currents, unless
some new structure or material can be found to keep the leaking under
control.

Deep sub-micron processes leak like sieves, yes, but that's a different
issue than what you raise above.

The increase in speed has always been dramatic and because the trend has
lasted 25 years, we expect it to continue as a matter of course.

"We"?? LOL Face the facts. *We* are fetting periously close to atomic
dimensions and the voltage gadients are constantly flirting with the MV/cm
"limit". *Wee* now have 100A on a chip, not much bigger across than the
wire supplying power to your eletric stove. ...and the current is alll on
the "surface". The power density of these things are on the order of a
*BILLION* times that of ol' Sol. Another 25 years? I'm glad I'm not
going to be the one whipped into producing that fantasy. ;-)

Ten years ago or so I was thrown into studying parallel computing; it was
said that the trend in speed surely couldn't continue. Now this field
has matured and there many really nice parallel algorithms, but the
problem it that it's a niche field; the systems were/are expensive and
manufacturer specific, not really suitable for standard software
products. I often spent more time 'parallizing' than on the problem I
wished to solve. Moreover, the resulting programs became 'solidified'
and virtually un-maintainable. Nevertheless, I learned many small habits
which might help in a pipelined environment, such as e.g. unrolling and
looping matrix multiplications the best way round.

??? Where did this change-of-subject come from?

--
Keith

That I haven't answered is no indication that I agree with you. It just
means that I've given up.

Ah, so I get the last word?

--
Keith

On Thu, 28 Oct 2004 21:36:22 -0400, keith wrote:

On Thu, 28 Oct 2004 18:06:37 +1000, Franc Zabkar wrote:

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

Curious... How are you going to measure the device power/current?

I suppose you could get a rough idea by monitoring the power
consumption on the AC side with a wattmeter. Of course this figure
would be influenced by the PSU's efficiency, but you could estimate
this by testing with a fixed resistive load on the +5V rail, say. For
example, if adding a 20W DC load drew an additional 25W from the
mains, then the PSU's efficiency would be 80%.

Forget the efficiency (which is not a constant). How do you shut down the
clocks to the CPU without "suspending" the rest of the system? Theidea
here is to measure the CPU, or more precisely the technology, not the
entire system. To do that the processor power has to be isolated. While
this certainly can be done, it's not something a casual user could do.

Hmm, my new (relatively) ISP screws up my newsfeed again as usual. I
don't see where Keith asked the original question.

But well, you know my age old project that never took off the ground
due to the various constraints. So part of that included a bridge bit
where we could plug in a PSU and split out the different rails for
measuring current. So what we thought we could do was to use it and
measure the +12V going to the processor since as far as I'm aware (my
fault if wrong, since I do most of the internet research), they are
supposed to feed the P4 from the +12V only.

The last time we tried it, when processor load goes up, the +5V
current doesn't move. The 3.3V and +12V moved. But since the 3.3V
supplies the RAM, it would make sense that when processing stuff, the
3.3V draw will increase.

So we would have isolate the +12V mostly. I got the Infineon spec pdf
for the power mosfet (hey I knew all that hanging around in S.E.B. was
going to come in handy!) on his motherboard. So we can account for
losses due to the conversion inefficiency.

Then we planned to swap the graphic cards, # of RAM modules, as well
as run the system without a processor to determine as far as we can,
what's being used by the rest of the system.

On top of that I figured that the system power draw should be
relatively constant, so S + CPU_Dyn + CPU_Leak = X. Since we can
control the VCore, the ClockSpeed, I thought we might be able to do
enough variations to calculate the different parts somehow.

Like I said, it's just for sating curiousity so I think it's good
enough accuracy. I'm not trying to engineer a processor or motherboard
or something! pPpP

--
L.Angel: I'm looking for web design work.
If you need basic to med complexity webpages at affordable rates, email me
Standard HTML, SHTML, MySQL + PHP or ASP, Javascript.
If you really want, FrontPage & DreamWeaver too.
But keep in mind you pay extra bandwidth for their bloated code

On Sun, 24 Oct 2004 07:16:24 GMT,
(The little lost angel) put
finger to keyboard and composed:

Reading, googling and all that, I get formulas and statement that
generally say that

Total Power = Dynamic Power + Static + Leakage + Short Circuit

I don't claim to have any significant knowledge in this area, but the
tutorial document you refer to
(http://www.cse.psu.edu/~vijay/iscatu...al-sources.pdf) does
not mention static power.

Instead it states that...

Total Power = Dynamic Power + Short Circuit + Leakage

P = C x Vdd^2 x P0-1 x f
+ tsc x Vdd x Ipeak x P0-1 x f
+ Vdd x Ileakage

AFAICS, the term P0-1 represents signal activity and is the
probability that a gate will change state. No signal activity would
mean that P0-1 = 0 and hence dynamic and SC power would be zero.

I've done some reading myself and collected a whole bunch of
references which generally state that static power and leakage power
are the same thing. Only one distinguishes between the two, but the
explanation is a bit sparse. So I confess I'm confused on this point.

Here are some of the online documents I managed to find:

http://www.elecdesign.com/Articles/A...8494/8494.html

"An intellectual-property (IP) platform reduces dynamic and static
(leakage) power in mobile chips built on generic 130-nm process
technologies."

http://www.ece.utexas.edu/~adnan/vls...18LowPower.ppt

Static power = leakage power

http://www.imm.dtu.dk/~s973591/

"The continuous miniaturization of VLSI-circuits is driven by a demand
for higher circuit speeds and lower power consumption. But as a result
of the lower supply voltages sub-threshold leakage currents become
significant. Transistors are no longer completely turned off but leak
continuously and static power consumption is therefore no longer
negligible in 90 nm and smaller processes. Leakage power has been
reported to be as much as 50% of total power consumption in actual
chips produced."

http://csdl.computer.org/comp/mags/c...2/rz068abs.htm

"Off-state leakage is static power, current that leaks through
transistors even when they are turned off."

http://www.imm.dtu.dk/~stassen/Proje...M/lpdesign.htm

"Static power consumption ... is caused by leakage currents while the
circuit is idle, i.e. not performing computations."

http://www.ohiolink.edu/etd/view.cgi?ucin982010436

"The leakage current, which leads to static power is becoming an
increasingly important part of the power dissipation."

http://arstechnica.com/articles/paed...prescott.ars/2

"To sum up the quote above, the amount of power dissipation due to
leakage current is 44% higher in the P-III 1.13 GHz than in the P-III
1.0 GHz. In other words, taking the same chip and upping the clock
speed also significantly increase the total leakage current flowing
through the chip.

The overall problem is that leakage current has been increasing at a
much faster rate than dynamic current, or the current that flows
through the transistors when they're in the "on" position. If this
trend continues, it will lead to a situation where the leakage current
begins to approach the dynamic current;"

http://www.citris-uc.org/projmatrix/...?project.id=63

"In nanometer scale CMOS technologies, static power consumption will
be the major component of the overall power consumption. Static power
has been rapidly growing as technologies have scaled supply voltage
VDD and threshold voltage Vth down to maintain drive current and
reduce dynamic power consumption, at the cost of an exponential
increase in transistor leakage currents. Static power can be as much
as 20% of the power budget of current highend microprocessors, and
this will likely increase as future technologies continue to reduce
Vth."

http://www.lowpower.de/charter/designguide_2.php

This chapter gives an overview of the sources of power consumption. A
formula for average power is given in equation 1.

equation 1: Pavg = Pdynamic + Pshort + Pleakage + Pstatic

V^3 dependency for dynamic power:
http://www.intel.com/technology/itj/..._awareness.htm
http://books.nap.edu/html/embedded_e...re/ch2_b3.html


- Franc Zabkar
--
Please remove one 's' from my address when replying by email.

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd. The
only cubic dependency is for dynamic power (see my other post in this
thread). It's all very confusing ...


- Franc Zabkar
--
Please remove one 's' from my address when replying by email.

On Thu, 28 Oct 2004 21:36:22 -0400, keith put finger
to keyboard and composed:

On Thu, 28 Oct 2004 18:06:37 +1000, Franc Zabkar wrote:

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

Curious... How are you going to measure the device power/current?

I suppose you could get a rough idea by monitoring the power
consumption on the AC side with a wattmeter. Of course this figure
would be influenced by the PSU's efficiency, but you could estimate
this by testing with a fixed resistive load on the +5V rail, say. For
example, if adding a 20W DC load drew an additional 25W from the
mains, then the PSU's efficiency would be 80%.

Forget the efficiency (which is not a constant).

That may be true if the PSU is operating at low power, but the
efficiency would be fairly constant if the PSU were operating near its
rated load. In any case, one could measure the AC power draw at DC
increments of 5W, 10W, 15W, and 20W, say, and then extrapolate one's
results to 0W. This non-linear (?) calibration curve could then be
used to accurately estimate the increased DC load (of the entire
system) resulting from changes in frequency or Vcore, for example. In
fact one could go the whole hog and measure the PSU's AC power
consumption at DC loads from 0W to 400W, say.

How do you shut down the
clocks to the CPU without "suspending" the rest of the system? Theidea
here is to measure the CPU, or more precisely the technology, not the
entire system. To do that the processor power has to be isolated. While
this certainly can be done, it's not something a casual user could do.

That's why I said "you could get a rough idea". My intention was
merely to suggest a non-intrusive method that a "casual user could
do". The assumption (right or wrong) was that the CPU would be
responsible for the majority of the increase in power consumption.
IMO, the most accurate method would involve measuring the voltage
across the current sensing element(s) in the Vcore regulator. Some
regulators appear to use resistive links, while others use the RDSon
resistance of a MOSFET. The latter may be hard to quantify.


- Franc Zabkar
--
Please remove one 's' from my address when replying by email.

On Sat, 30 Oct 2004 06:12:09 +1000, Franc Zabkar wrote:

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd.

Leakage current, particularly gate tunneling, goes up by at *least* the
square of the voltage, this power goes as the cube. Sub-threshold current
is a similar issue. Think about the power dissipated in a diode, as it's
forward bias increase. Leakage is worse.

The only cubic dependency is for dynamic power (see my other post in this
thread).

Nope. Dynamic power goes with the square of the voltage. Think of a
CMOS switch as a charge pump. The charge goes up linearly with the
voltage, thus the power as the square.

It's all very confusing ...

Apparently. This is new territory for many.

--
Keith

"Franc Zabkar" wrote in message
...
On Sun, 24 Oct 2004 07:16:24 GMT,
(The little lost angel) put
finger to keyboard and composed:

Reading, googling and all that, I get formulas and statement that
generally say that

Total Power = Dynamic Power + Static + Leakage + Short Circuit

I don't claim to have any significant knowledge in this area, but the
tutorial document you refer to
(http://www.cse.psu.edu/~vijay/iscatu...al-sources.pdf) does
not mention static power.

Instead it states that...

Total Power = Dynamic Power + Short Circuit + Leakage

P = C x Vdd^2 x P0-1 x f
+ tsc x Vdd x Ipeak x P0-1 x f
+ Vdd x Ileakage

AFAICS, the term P0-1 represents signal activity and is the
probability that a gate will change state. No signal activity would
mean that P0-1 = 0 and hence dynamic and SC power would be zero.

I've done some reading myself and collected a whole bunch of
references which generally state that static power and leakage power
are the same thing. Only one distinguishes between the two, but the
explanation is a bit sparse. So I confess I'm confused on this point.


Actually, the VJ's article does mention "static" power, on Page1,
slide 2. For the overall power, the "leakage" and "static" can
be considered as same since they both are frequency-independent.
The difference between them is that the leakage is a parasitic
by accident (or by nature of transistor shrinking if you prefer),
while the "static" power is by circuit design. One example is
pseudo-nMOS circuits designed to speed up gates, see e.g.

http://www.ece.utexas.edu/~adnan/vls...ctFamilies.ppt

The main page has some other important information on the topic,
e.g. Slide 12 of
http://www.ece.utexas.edu/~adnan/vls...18LowPower.ppt

If you check the above page, you will find again that for
most practical purposes the leakage current is considered
by modern engineering as being Vdd-independent. Therefore
the CPU quiescent power (leakage + static) is linear with
Vdd. The quadratic, cubic, or exponential dependency is
a product of imagination of Mr. Keith. He confuses Vdd with
temperature, where the dependence is substantial. Because
of the temperature effect (and finite junction-to-case
resistance), an indirect increase in measured quiescent
current can sometimes be confused with the effect of Vdd.

Regards,
-aap

On Sat, 30 Oct 2004 22:04:04 -0400, keith put finger
to keyboard and composed:

On Sat, 30 Oct 2004 06:12:09 +1000, Franc Zabkar wrote:

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd.

Leakage current, particularly gate tunneling, goes up by at *least* the
square of the voltage, this power goes as the cube. Sub-threshold current
is a similar issue. Think about the power dissipated in a diode, as it's
forward bias increase. Leakage is worse.

The tutorial that was alluded to by the OP distinguishes between
static power and leakage power. All other references appear to equate
the two concepts, as you have done. I would think that in the "static"
state as many as half the transistors could be ON and therefore
drawing significant current. The rest would be OFF and drawing a
comparatively negligible leakage current????

The only cubic dependency is for dynamic power (see my other post in this
thread).

Nope. Dynamic power goes with the square of the voltage.

OK, so my statement was somewhat ambiguous. I meant that I found only
two online references that mentioned cubic dependency in relation to
power dissipation, and neither of these references talked about static
power or leakage, only dynamic power.

This is the first one:
http://www.intel.com/technology/itj/..._awareness.htm

The article discusses the Pentium M processor. It arrives at a cubic
dependency by assuming that frequency is proportional to Vcore. I
confess I don't understand the basis for this assumption.

This is the second article:
http://books.nap.edu/html/embedded_e...re/ch2_b3.html

It examines the effects on power dissipation in an existing design
when it is scaled to a new technology. A cubic dependency arises
because newer processes result in lower capacitances and a lower
Vcore.

Think of a
CMOS switch as a charge pump. The charge goes up linearly with the
voltage, thus the power as the square.

It's all very confusing ...

Apparently. This is new territory for many.

Well, I understand the concept of leakage from my Uni days, and I
understand how the formula for dynamic power is derived. In the latter
case the energy stored by a capacitor is 1/2 * C * V^2, and this
energy is moved twice during one clock cycle. So power = (1/2 * C *
V^2) * 2f = C * V^2 * f.

That only leaves the concept of static power as opposed to leakage
power. I don't understand why some references distinguish between the
two, and others do not. How do these parameters differ, ie what are
the mechanisms underlying static power as opposed to leakage?


- Franc Zabkar
--
Please remove one 's' from my address when replying by email.