Processor heat dissipation, Leakage current, voltages & clockspeed

I know I'm a bit slow to start looking up this since the Prescott
thrust the issue into lime light. I didn't quite follow the major
discussion some weeks back. My friend got himself a spanking new
Prescott and claims it wasn't that hot despite claims. Yet Intel did
cancel the 4Ghz version so it got me thinking again whether the heat
increases dramatically with clockspeed. Since leakage was the big
thing thrown about, whether that was what increased with clockspeed.
And whether we could do any experiments to test it out.

So I started doing some reading up mainly from the tutorial document
posted some time back. Tried to understand these issues but don't
think I got very far. Would appreciate it greatly if the resident
experts here point out where I might have understood it wrongly.

I don't understand most of the explanations for how these are
calculated (most of the documents assume proficiency with mathematical
symbology which every regular visitor here knows by now I suck at
PPpP). So here's my best effort at arriving at something useful to
me as a layperson who's interested only in getting a useful real world
approximation of how these things are, say x.x rather than x.xxxxxx
kind of accuracy PpP

Reading, googling and all that, I get formulas and statement that
generally say that

Total Power = Dynamic Power + Static + Leakage + Short Circuit

Dynamic power is directly related to clockspeed. Leakage doesn't care
about clockspeed and is a function of the process/technology but
appears to be in direct relation with temperature, i.e. hotter
processors will leak even more power?.

I got a bit confused with a graph that displaying Leakage current vs
Vgs. http://www.cse.psu.edu/~vijay/iscatu...al-sources.pdf
at pg 7. It seems to imply that lowering voltages will increase the
leakage??

Anyway, the point is, can I say that given the usual x86 processor.
The difference between the power dissipated at 3Ghz and at 4Ghz is
still mostly clockspeed.

Because dynamic power has to do with whether there's any actual
activity, both a 3Ghz and 4Ghz would have similar power draw when
idling since leakage will be there but dynamic would be very low.
While Static and Short are pretty much constant? Or would Short also
be directly related to the amount of activity since it's determined by
the slope of the signal so if there's no activity, there's no direct
current situation since there's no switching done.

So if we set the same (static becomes a constant) prescott at various
vcore (changes leakage right?), change the clockspeeds (changes
Dynamic), measure idle and load power dissipation, would we then be
able to calculate roughly the power used by Dynamic, Static, Short and
Leakage?

TiA!!!!

--
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On Sun, 24 Oct 2004 07:16:24 +0000, The little lost angel wrote:

I know I'm a bit slow to start looking up this since the Prescott
thrust the issue into lime light. I didn't quite follow the major
discussion some weeks back. My friend got himself a spanking new
Prescott and claims it wasn't that hot despite claims. Yet Intel did
cancel the 4Ghz version so it got me thinking again whether the heat
increases dramatically with clockspeed. Since leakage was the big
thing thrown about, whether that was what increased with clockspeed.
And whether we could do any experiments to test it out.

So I started doing some reading up mainly from the tutorial document
posted some time back. Tried to understand these issues but don't
think I got very far. Would appreciate it greatly if the resident
experts here point out where I might have understood it wrongly.

You likely didn't. ;-)

I don't understand most of the explanations for how these are
calculated (most of the documents assume proficiency with mathematical
symbology which every regular visitor here knows by now I suck at
PPpP). So here's my best effort at arriving at something useful to
me as a layperson who's interested only in getting a useful real world
approximation of how these things are, say x.x rather than x.xxxxxx
kind of accuracy PpP

Reading, googling and all that, I get formulas and statement that
generally say that

Total Power = Dynamic Power + Static + Leakage + Short Circuit

You're author uses some pretty strange terminology, but it's really
somewhat simpler (and more complicated than that. Very little in a
processor these days is what a your author would call "static". The
PLL would have its static aspects, and likely nothing else. The term
"static power" is considered to be "leakage".

"Short circuit" current, I've always heard called "shoot-through" and
lumped in with dynamic power, so your equation drops to two terms;
Dynamic and Static. ...not that these other things don't exist, they just
aren't that interesting to anyone other than the circuit designer.

Dynamic power is directly related to clockspeed.

And the square of the voltage. Note that the voltage may have to be
cranked up to get more GHz.

Leakage doesn't care
about clockspeed and is a function of the process/technology but appears
to be in direct relation with temperature, i.e. hotter processors will
leak even more power?.

Sure, and don't forget voltage. Leakage curent rises with something like
the square of the voltage (maybe even more), so static power rises by the
third power.

I got a bit confused with a graph that displaying Leakage current vs
Vgs. http://www.cse.psu.edu/~vijay/iscatu...al-sources.pdf at
pg 7. It seems to imply that lowering voltages will increase the
leakage??

What they're pointing out is that when one reduces the design-point
Vdd, one must compensate by reducing the threshold voltage of the devices
(Vt must be less than Vdd or the gate won't switch). Lower Vt devices have
a sub-threshold leakage far worse than higher Vt devices. A particular
device doesn't leak more at lower voltages, rather it's a side-effect of
the choice (need) to go to a lower Vt device.

Anyway, the point is, can I say that given the usual x86 processor. The
difference between the power dissipated at 3Ghz and at 4Ghz is still
mostly clockspeed.

No, one makes certain design/processing choices to enable 4GHz. These
choices lead to higher power dissipation. If you took your 4GHz device
and ran it at 3GHz, and at the same voltage, then the dynamic power
difference would be simply the "clock speed" (i.e. 3/4 dynamic power), but
still the full static/leakage power. You wouldn't have reduced the total
power by 3/4. Of course you don't need the full Vdd at reduced frequency,
so you may be able to reduce that, which will lower the dynamic power
further (by the square of Vdd1/Vdd2) and static power (by perhaps the
cube).

Because dynamic power has to do with whether there's any actual
activity, both a 3Ghz and 4Ghz would have similar power draw when idling
since leakage will be there but dynamic would be very low.

Exactly. If you want to measure leakage power, shut the processor clocks
off (put the processor to sleep).

While Static and Short are pretty much constant? Or would Short also be directly
related to the amount of activity since it's determined by the slope of
the signal so if there's no activity, there's no direct current
situation since there's no switching done.

Yes, what you're calling "short" is "shoot-through" and can be considered
a component of the dynamic power. Though it's not directly related to any
capacitance, it walks like a duck.

So if we set the same (static becomes a constant) prescott at various
vcore (changes leakage right?), change the clockspeeds (changes
Dynamic), measure idle and load power dissipation, would we then be able
to calculate roughly the power used by Dynamic, Static, Short and
Leakage?

If you vary clock speed only, the Y-intercept (clock = 0) point would
indicate the leakage. At least at this level, forget "short" and
"static" power terms and include "static" and "leakage" in the static
term, and "dynamic" and "short" in the dynamic term:

Total = dynamic + static



--
Keith

On Sun, 24 Oct 2004 09:41:42 -0400, keith wrote:

And the square of the voltage. Note that the voltage may have to be
cranked up to get more GHz.

Sure, and don't forget voltage. Leakage curent rises with something like
the square of the voltage (maybe even more), so static power rises by the
third power.

So both the dynamic power and static power rises exponentially to the
voltage applied? Thus if I take a 3Ghz Prescott, changes the voltage
from say 1.4V to 1.5V and measure an increase of 5W power while idle,
this would imply that the increase in leakage current is 500A!?? Since
the current increases with the square, so 5W = 0.1*0.1 * A therefore 5
/ 0.01 = A = 500A? At cube, it becomes even crazier

Ok, I did that before I saw the formula you gave later as (VDD1/VDD2),
thus is it (1.4/1.5)^3 * A = 5, hence A= 6.15 which sounds a WHOLE lot
more credible. Would this also mean that the actual leakage can be
1.5V x 6.15A = 9W or would it be 1.5V x (6.15A + X) where X was the
original leakage current at 1.4V?

Please don't laugh too hard if the maths is hopelessly naive & wrong
PPPP


What they're pointing out is that when one reduces the design-point
Vdd, one must compensate by reducing the threshold voltage of the devices
(Vt must be less than Vdd or the gate won't switch). Lower Vt devices have
a sub-threshold leakage far worse than higher Vt devices. A particular
device doesn't leak more at lower voltages, rather it's a side-effect of
the choice (need) to go to a lower Vt device.

Hmm, I'm getting a little confused (as usual). Maybe it's because I
don't truly understand what's Vdd and Vt. Am I correct to understand
that Vdd is what's commonly known as VCore, i.e 1.4V for the Prescott,
while Vtt is some internal design parameter that we will not know, e.g
1.3V for the Prescott. Therefore if they attempted to drop the VCore
to say 1.2V and therefore drop the internal Vt to say 1.1V to
compensate, the leakage problem will increase even though the voltages
had dropped?

How would this play out with the decrease in leakage current since
voltage dropped and leakage responds exponentially to that? Can it be
said that theoretically it can be designed so that the decrease in
leakage from the voltage drop cancels out the increase in sub
threshold leakage so that using a lower Vdd/Vt won't hurt in terms of
leakage current and therefore help lower the total power dissipation
since dynamic power will be drastically reduced with lower VCore/Vdd?

Would this Vt/Vdd issue be also the reason for the popular practise of
raising VCore to get higher clockspeeds for the overclockers. Since
it's been mentioned higher voltages help transistors switch faster.
i.e. the transistors cannot switch faster at the default Vt say 1V and
in order to do say 4Ghz, it needs to up Vt to say 1.35V and at the
default VCore of 1.4V, the difference isn't big enough to allow this.
Hnece raising VCore to 1.5V then allows the overclocker to overcome
the designed Vdd/Vt limits?

Exactly. If you want to measure leakage power, shut the processor clocks
off (put the processor to sleep).

Is this the same as the normal idling mode or would it be a special
function that can be enabled by software i.e. sending a particular
instruction to the processor and see the PC stop responding? Or would
we get a good approximation by compiling a small asm program running
in DOS (or maybe some bare minimum linux kernel to minimize OS
interference) that does nothing except endless loop of HLT? Since
googling about this imply that HLT only puts the processor to sleep
until the next interrupt. This would be relatively often due to the
real time clock interrupt isn't it?

If you vary clock speed only, the Y-intercept (clock = 0) point would
indicate the leakage. At least at this level, forget "short" and
"static" power terms and include "static" and "leakage" in the static
term, and "dynamic" and "short" in the dynamic term:
Total = dynamic + static

Thanks for making it simpler & clearer!!! *hugz*

Now to figure out a way to make it clock=0 so that I can sate my
curiousity :PpPpP

--
L.Angel: I'm looking for web design work.
If you need basic to med complexity webpages at affordable rates, email me
Standard HTML, SHTML, MySQL + PHP or ASP, Javascript.
If you really want, FrontPage & DreamWeaver too.
But keep in mind you pay extra bandwidth for their bloated code

In article , a?n?g?e?
says...
On Sun, 24 Oct 2004 09:41:42 -0400, keith wrote:

And the square of the voltage. Note that the voltage may have to be
cranked up to get more GHz.

Sure, and don't forget voltage. Leakage curent rises with something like
the square of the voltage (maybe even more), so static power rises by the
third power.

So both the dynamic power and static power rises exponentially to the
voltage applied? Thus if I take a 3Ghz Prescott, changes the voltage
from say 1.4V to 1.5V and measure an increase of 5W power while idle,
this would imply that the increase in leakage current is 500A!?? Since
the current increases with the square, so 5W = 0.1*0.1 * A therefore 5
/ 0.01 = A = 500A? At cube, it becomes even crazier

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

Ok, I did that before I saw the formula you gave later as (VDD1/VDD2),
thus is it (1.4/1.5)^3 * A = 5, hence A= 6.15 which sounds a WHOLE lot
more credible. Would this also mean that the actual leakage can be
1.5V x 6.15A = 9W or would it be 1.5V x (6.15A + X) where X was the
original leakage current at 1.4V?

I still don't follow your variables (what's 'A'?), though yes, the
dynamic power is proportional to the frequency and voltage squared, so
you can't take the absolute voltage, rather the change in voltage.

Please don't laugh too hard if the maths is hopelessly naive & wrong
PPPP

Laugh? teehee ;-)

What they're pointing out is that when one reduces the design-point
Vdd, one must compensate by reducing the threshold voltage of the devices
(Vt must be less than Vdd or the gate won't switch). Lower Vt devices have
a sub-threshold leakage far worse than higher Vt devices. A particular
device doesn't leak more at lower voltages, rather it's a side-effect of
the choice (need) to go to a lower Vt device.

Hmm, I'm getting a little confused (as usual). Maybe it's because I
don't truly understand what's Vdd and Vt. Am I correct to understand
that Vdd is what's commonly known as VCore, i.e 1.4V for the Prescott,

Yes.

while Vtt is some internal design parameter that we will not know, e.g
1.3V for the Prescott. Therefore if they attempted to drop the VCore
to say 1.2V and therefore drop the internal Vt to say 1.1V to
compensate, the leakage problem will increase even though the voltages
had dropped?

Your numbers are way off for Vt, but essentially yes. Vt is the
voltage that must be applied between the gate and source for the
transistor to turn "on". This is a device design parameter. Obviously
if this "threshold" (line between "on" and "off") voltage is higher
than the core voltage, the device is rather useless (can never be
turned on).

How would this play out with the decrease in leakage current since
voltage dropped and leakage responds exponentially to that? Can it be
said that theoretically it can be designed so that the decrease in
leakage from the voltage drop cancels out the increase in sub
threshold leakage so that using a lower Vdd/Vt won't hurt in terms of
leakage current and therefore help lower the total power dissipation
since dynamic power will be drastically reduced with lower VCore/Vdd?

One can play all sorts of games balancing power, however the device
still has to function and be marketable. Lowering Vt tends to make the
devices faster, though more leaky. One can drop the Vcore (Vdd, where
'd' = drain) to compensate, but the circuit gets slower again. There
are all sorts of knobs to twist and many counteract others. The trick
is to find the right mix of knob settings.

Would this Vt/Vdd issue be also the reason for the popular practise of
raising VCore to get higher clockspeeds for the overclockers. Since
it's been mentioned higher voltages help transistors switch faster.

It's not so much that Vt is important here, but yes a higher Vcore
raises the current so capacitors charge faster. It also raises the
power = temperature.

i.e. the transistors cannot switch faster at the default Vt say 1V and
in order to do say 4Ghz, it needs to up Vt to say 1.35V and at the
default VCore of 1.4V, the difference isn't big enough to allow this.
Hnece raising VCore to 1.5V then allows the overclocker to overcome
the designed Vdd/Vt limits?

Vt is a design parameter and really doesn't have all that much to do
with over-clocking. It's locked into the design by the device physics;
raising Vdd doesn't change Vt. It does make circuits faster because of
the higher charging current.

Exactly. If you want to measure leakage power, shut the processor clocks
off (put the processor to sleep).

Is this the same as the normal idling mode or would it be a special
function that can be enabled by software i.e. sending a particular
instruction to the processor and see the PC stop responding? Or would
we get a good approximation by compiling a small asm program running
in DOS (or maybe some bare minimum linux kernel to minimize OS
interference) that does nothing except endless loop of HLT? Since
googling about this imply that HLT only puts the processor to sleep
until the next interrupt. This would be relatively often due to the
real time clock interrupt isn't it?

Either will approximate this. However there are still clocks going to
the caches and bus logic (for cache snoops) in these modes. Some deep-
sleep modes (perhaps hybernation or suspend-to-disk) may shut down the
clocks. You'd have to consult the specs of the processor/system to be
sure.

If you vary clock speed only, the Y-intercept (clock = 0) point would
indicate the leakage. At least at this level, forget "short" and
"static" power terms and include "static" and "leakage" in the static
term, and "dynamic" and "short" in the dynamic term:
Total = dynamic + static

Thanks for making it simpler & clearer!!! *hugz*

Now to figure out a way to make it clock=0 so that I can sate my
curiousity :PpPpP

Curious... How are you going to measure the device power/current?

--
Keith

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

Curious... How are you going to measure the device power/current?

I suppose you could get a rough idea by monitoring the power
consumption on the AC side with a wattmeter. Of course this figure
would be influenced by the PSU's efficiency, but you could estimate
this by testing with a fixed resistive load on the +5V rail, say. For
example, if adding a 20W DC load drew an additional 25W from the
mains, then the PSU's efficiency would be 80%.


- Franc Zabkar
--
Please remove one 's' from my address when replying by email.

On Thu, 28 Oct 2004 18:06:37 +1000, Franc Zabkar wrote:

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

Curious... How are you going to measure the device power/current?

I suppose you could get a rough idea by monitoring the power
consumption on the AC side with a wattmeter. Of course this figure
would be influenced by the PSU's efficiency, but you could estimate
this by testing with a fixed resistive load on the +5V rail, say. For
example, if adding a 20W DC load drew an additional 25W from the
mains, then the PSU's efficiency would be 80%.

Forget the efficiency (which is not a constant). How do you shut down the
clocks to the CPU without "suspending" the rest of the system? Theidea
here is to measure the CPU, or more precisely the technology, not the
entire system. To do that the processor power has to be isolated. While
this certainly can be done, it's not something a casual user could do.

--
Keith

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd. The
only cubic dependency is for dynamic power (see my other post in this
thread). It's all very confusing ...


- Franc Zabkar
--
Please remove one 's' from my address when replying by email.

On Sat, 30 Oct 2004 06:12:09 +1000, Franc Zabkar wrote:

On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd.

Leakage current, particularly gate tunneling, goes up by at *least* the
square of the voltage, this power goes as the cube. Sub-threshold current
is a similar issue. Think about the power dissipated in a diode, as it's
forward bias increase. Leakage is worse.

The only cubic dependency is for dynamic power (see my other post in this
thread).

Nope. Dynamic power goes with the square of the voltage. Think of a
CMOS switch as a charge pump. The charge goes up linearly with the
voltage, thus the power as the square.

It's all very confusing ...

Apparently. This is new territory for many.

--
Keith

"Franc Zabkar" wrote in message
...
On Wed, 27 Oct 2004 12:12:21 -0400, Keith R. Williams
put finger to keyboard and composed:

I don't follow your numbers at all. The change from 1.4V to 1.5V is 7%
(1.4V * 1.07 = 1.5), so the dynamic power will change by the square of
7% (1.07 * 1.07) or about 15%. The static power (assume a cube) would
change by about 22% (1.07 * 1.07 * 1.07).

All but one of the online references I have found state that static
power = leakage power. None talk about a cubic dependency on Vdd. The
only cubic dependency is for dynamic power (see my other post in this
thread). It's all very confusing ...


Franc, the cubic dependence in Intel's formulas is because
they are talking broadly about future power envelops, and
they assumed that the top frequency of a processor family is
approximately proportional to supplied voltage Vdd.
When factored with standard (Vdd)^2 dependence for dynamic
power, they have (Vdd)^3, but the frequency is excluded.

Hope this clears the cubic issue.

Regards,

- aap

On Wed, 27 Oct 2004 03:34:01 GMT,
(The little lost angel) put
finger to keyboard and composed:

So both the dynamic power and static power rises exponentially to the
voltage applied? Thus if I take a 3Ghz Prescott, changes the voltage
from say 1.4V to 1.5V and measure an increase of 5W power while idle,
this would imply that the increase in leakage current is 500A!?? Since
the current increases with the square, so 5W = 0.1*0.1 * A therefore 5
/ 0.01 = A = 500A? At cube, it becomes even crazier

Ok, I did that before I saw the formula you gave later as (VDD1/VDD2),
thus is it (1.4/1.5)^3 * A = 5, ...

VDD1/VDD2 is a dimensionless quantity. Hence the units on both sides
of your equation do not balance, ie on the left you have amps, while
on the right you have watts. Then there's your mistake in equating
ratiometric changes with absolute ones ...

... hence A= 6.15 which sounds a WHOLE lot
more credible. Would this also mean that the actual leakage can be
1.5V x 6.15A = 9W or would it be 1.5V x (6.15A + X) where X was the
original leakage current at 1.4V?

Please don't laugh too hard if the maths is hopelessly naive & wrong
PPPP


- Franc Zabkar
--
Please remove one 's' from my address when replying by email.