A computer components & hardware forum. HardwareBanter

If this is your first visit, be sure to check out the FAQ by clicking the link above. You may have to register before you can post: click the register link above to proceed. To start viewing messages, select the forum that you want to visit from the selection below.

Go Back   Home » HardwareBanter forum » Processors » General
Site Map Home Register Authors List Search Today's Posts Mark Forums Read Web Partners

First Next-Gen CELL Processor: 2 PPEs - 32 SPEs - at least 1 Teraflop



 
 
Thread Tools Display Modes
  #1  
Old December 7th 06, 07:03 PM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,comp.sys.super,comp.sys.powerpc.tech
AirRaid
external usenet poster
 
Posts: 126
Default First Next-Gen CELL Processor: 2 PPEs - 32 SPEs - at least 1 Teraflop

http://www.beyond3d.com/forum/showthread.php?t=36335

latest Cell Roadmap
http://img445.imageshack.us/img445/7706/cell2007pw6.jpg

"During a recent event IBM has unveiled a few details on Cell
roadmap.As you can see Cell will be manufactured at 65nm during next
year and a next gen version of the chip is expected around 2010
featuring 2PPE and 32 SPEs (45nm manufacturing technology)."
__________________________________________________ _____________________________

this backs Jim Kahle (IBM's Chief Cell Architect) recent claim that
they'd be aiming for 1 TeraFlop performance on a single chip using 32
SPEs


http://blogs.mercurynews.com/aei/200...aystation.html

"JK: For us to extrapolate. We will push the number of special
processing units. By 2010, we will shoot for a teraflop on a chip. I
think it establishes there is a roadmap. We want to invest in it. For
those that want to invest in the software, it shows that there is life
in this architecture as we continue to move forward.

DT: Right now you're at 200 gigaflops?

JK: We're in the low 200s now.

DT : So that is five times faster by 2010?

JK: Four or five times faster. Yes, you basically need about 32 special
processing units."

  #2  
Old December 9th 06, 01:37 PM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,comp.sys.super,comp.sys.powerpc.tech
[email protected]
external usenet poster
 
Posts: 4
Default First Next-Gen CELL Processor: 2 PPEs - 32 SPEs - at least 1 Teraflop

AirRaid wrote:
this backs Jim Kahle (IBM's Chief Cell Architect) recent claim that
they'd be aiming for 1 TeraFlop performance on a single chip using 32
SPEs


What I want to know is if they're ever going to make a chip that
concentrates on *double precision* (64-bit) floating-point performance.

John Savard

  #3  
Old December 9th 06, 09:32 PM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,comp.sys.super,comp.sys.powerpc.tech
Jason Lee Eckhardt
external usenet poster
 
Posts: 1
Default First Next-Gen CELL Processor: 2 PPEs - 32 SPEs - at least 1 Teraflop

In article om,
wrote:
AirRaid wrote:
this backs Jim Kahle (IBM's Chief Cell Architect) recent claim that
they'd be aiming for 1 TeraFlop performance on a single chip using 32
SPEs


What I want to know is if they're ever going to make a chip that
concentrates on *double precision* (64-bit) floating-point performance.


Yes, they will.
Just yesterday at a lecture at Rice University, Andy White of LANL
discussed the RoadRunner system being developed around Opteron and
Cell. As part of the talk, he showed a roadmap for Cell which
has an enhanced version scheduled for early 2008 with better
double-precision performance (~100 GFLOP/s). That is the one that
will be in the production RoadRunner, if I understood him correctly.

Even with the current Cell (~15 DP GFLOP/s), Andy said they were
getting 5X speed-up on Sweep3D (hand tuned for Cell) over Opteron.
Sweep3D is the core of one of their large production codes and
uses double precision for all FP. That is good DP performance.

He mentioned that 2-3 other important production apps were expected
to do well on Cell, though they had done only the preliminary analysis
and not the actual ports yet.

 




Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

vB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Forum Jump

Similar Threads
Thread Thread Starter Forum Replies Last Post
Cell Architect Jim Kahle: ~1 Teraflop on a chip by 2010.... so PS4 will be maybe a little more than that ? AirRaid Nvidia Videocards 0 October 26th 06 07:38 PM
Interview With Cell Architect Jim Kahle - 1 Teraflop on a chip by 2010 AirRaid General 0 October 26th 06 07:26 PM
EE Times article on the CELL workstation, PS3 gOJDO General 3 March 12th 06 09:32 PM
WINNER MULTIMEDIA MONSTER: Cell's nine processors make it a gOJDO General 0 March 12th 06 06:31 PM
WINNER MULTIMEDIA MONSTER: Cell's nine processors make it a gOJDO General 0 March 12th 06 06:31 PM


All times are GMT +1. The time now is 08:46 AM.


Powered by vBulletin® Version 3.6.4
Copyright ©2000 - 2024, Jelsoft Enterprises Ltd.
Copyright ©2004-2024 HardwareBanter.
The comments are property of their posters.