8x8, 16x16, 1M x 36 P -ram memories

What would this mean by the ram memories, it's showing some bit
informations on every module (8x8, 16x16, 1Mx36P), and the
infrastructure of ram memory modules, but informationally for a base to
start a wikipedia dig up, what the heck is it ?

mm

Majki Majk wrote:
What would this mean by the ram memories, it's showing some bit
informations on every module (8x8, 16x16, 1Mx36P), and the
infrastructure of ram memory modules, but informationally for a base to
start a wikipedia dig up, what the heck is it ?

mm

If that information is used to describe a single chip, it can have
some meaning. For example, 1Mx36P might suggest a chip suited
for embedded applications, rather than desktop computers. It
would consist of an array of 1 million locations by 32 bits wide,
with an extra 4 bits suitable for parity per byte lane (one
bit per lane).

But when an array description is applied to a DIMM, rather than
a chip, it doesn't tell you as much. It is possible that
several difference chip solutions could be used, so you
don't know what you're really getting. If I tell you
128Mx64, there would be more than one way of building that,
and the differences could be significant to me.

JEDEC has, over the years, attempted to instruct the companies
in the industry, how to describe memory. But many in the industry
feel that inaccurate descriptions are just fine, and work to their
advantage.

Paul

Paul wrote:
Majki Majk wrote:
What would this mean by the ram memories, it's showing some bit
informations on every module (8x8, 16x16, 1Mx36P), and the
infrastructure of ram memory modules, but informationally for a base
to start a wikipedia dig up, what the heck is it ?

mm

If that information is used to describe a single chip, it can have
some meaning. For example, 1Mx36P might suggest a chip suited
for embedded applications, rather than desktop computers. It
would consist of an array of 1 million locations by 32 bits wide,
with an extra 4 bits suitable for parity per byte lane (one
bit per lane).

But when an array description is applied to a DIMM, rather than
a chip, it doesn't tell you as much. It is possible that
several difference chip solutions could be used, so you
don't know what you're really getting. If I tell you
128Mx64, there would be more than one way of building that,
and the differences could be significant to me.

JEDEC has, over the years, attempted to instruct the companies
in the industry, how to describe memory. But many in the industry
feel that inaccurate descriptions are just fine, and work to their
advantage.

Paul

Aha. Seems brighter look now. This numbers sometimes confused me.