P1-P55T2P4 L2-cache - memory upgrad question?

On a P1-P55T2P4 Rev 3 with a Pentium 166 MHz and 64 MB RAM I wanted
installed another 64 MB which I saved from being thrown away. The board has
a TAG-RAM socket empty and no Pipelined Burst Level 2 Cache Expansion Slot
socket installed. I took an old TAG-RAM from another Pentium board,
installed into the TAG-RAM socket. JP4 cacheable size on Postion 512 MB.
When in position 64MB - system becomes unstable.
There are chips installed in the position called 256/512 onboard L2 cache in
the manual. L2 cache enabled in BIOS.

Problems:
1. I could not find any improvement in speed under Win98SE just by the feel,
no checks run. I had another GIGABYTE 586HX... years ago, the upgrade in
memory and adding the TAG-RAM improved performance speed drastically.
2. When checking with CPUID - there was no L2 cache detected whatsoever.

Any idea what can be wrong?

Viktor Weisshäupl
if personal email, please to weisshaeupl at uta dot at
address in posting exists, but is never read and only meant as a spam
container

viktor weisshaeupl schrieb:

On a P1-P55T2P4 Rev 3 with a Pentium 166 MHz and 64 MB RAM I wanted
installed another 64 MB which I saved from being thrown away. The board has
a TAG-RAM socket empty and no Pipelined Burst Level 2 Cache Expansion Slot
socket installed. I took an old TAG-RAM from another Pentium board,
installed into the TAG-RAM socket. JP4 cacheable size on Postion 512 MB.
When in position 64MB - system becomes unstable.
There are chips installed in the position called 256/512 onboard L2 cache in
the manual. L2 cache enabled in BIOS.

Problems:
1. I could not find any improvement in speed under Win98SE just by the feel,
no checks run. I had another GIGABYTE 586HX... years ago, the upgrade in
memory and adding the TAG-RAM improved performance speed drastically.
2. When checking with CPUID - there was no L2 cache detected whatsoever.

Any idea what can be wrong?

I'd run ctcm (not the Creative tool, the c't cache/memory benchmark) and
see what that says in terms of cacheable area.

Stephan
--
Meine Andere Seite: http://stephan.win31.de/
PC#6: i440BX, 1xP3-500E, 512 MiB, 18+80 GB, R9k AGP 64 MiB, 110W
This is a SCSI-inside, Legacy-plus, TCPA-free computer
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Bonjour,

viktor weisshaeupl a écrit :

On a P1-P55T2P4 Rev 3 with a Pentium 166 MHz and 64 MB RAM I wanted
installed another 64 MB which I saved from being thrown away. The
board has a TAG-RAM socket empty and no Pipelined Burst Level 2 Cache
Expansion Slot socket installed. I took an old TAG-RAM from another
Pentium board, installed into the TAG-RAM socket. JP4 cacheable size
on Postion 512 MB. When in position 64MB - system becomes unstable.
There are chips installed in the position called 256/512 onboard L2
cache in the manual. L2 cache enabled in BIOS.

Have you checked here :
http://www.jump.net/~lcs/kalle/rev3.htm#TAG

I remember that I had upgraded my T2P4 rev 3 to 128Mb some years ago
simply by adding a single "standard 32K X 8 15ns Static RAM" bought in a
"radio-shake" like for 2-3$ and put it in the right socket to get all
the system analysers reports more than 64Mo cachable (don't remember
exactly, may be 512Mo).
By the way all the benchmarks were reflecting correctly wether or not I
use that additionnal TagRam.