Intel's New Weapons: Pentium 4 E (Prescott)

Hi,

Reviews so far. . . .

Anandtech: Intel's Pentium 4 E: Prescott Arrives with Luggage
http://tinyurl.com/yuqml

Tomshardwa Intel's New Weapons: Pentium 4 Prescott
http://tinyurl.com/2cd45

--
Wayne ][
new specs coming soon!

Wayne Youngman wrote:
Hi,

Reviews so far. . . .

Anandtech: Intel's Pentium 4 E: Prescott Arrives with Luggage
http://tinyurl.com/yuqml

Tomshardwa Intel's New Weapons: Pentium 4 Prescott
http://tinyurl.com/2cd45


And a few mo

http://hardocp.com/article.html?art=NTgz
http://hothardware.com/hh_files/CCAM...t_p4ee34.shtml
http://www.lostcircuits.com/cpu/prescott/


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Makes you wonder what all the fuss was about.

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"Wayne Youngman" wrote in message
...
Hi,

Reviews so far. . . .

Anandtech: Intel's Pentium 4 E: Prescott Arrives with Luggage
http://tinyurl.com/yuqml

Tomshardwa Intel's New Weapons: Pentium 4 Prescott
http://tinyurl.com/2cd45

--
Wayne ][
new specs coming soon!

Thanks for posting the links. One question, however, about the Anandtech
review. Why does the writer think that a a micro-op is only one byte long,
and see the 64 KByte AMD instruction cache as necessarily larger than the
Intel 12 Kmicro-op cache? As far as I know, the rest of the review may be
spot on, but this item does make me wonder.

--
Phil Weldon, pweldonatmindjumpdotcom
For communication,
replace "at" with the 'at sign'
replace "mindjump" with "mindspring."
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"Wayne Youngman" wrote in message
...
Hi,

Reviews so far. . . .

Anandtech: Intel's Pentium 4 E: Prescott Arrives with Luggage
http://tinyurl.com/yuqml

Tomshardwa Intel's New Weapons: Pentium 4 Prescott
http://tinyurl.com/2cd45

--
Wayne ][
new specs coming soon!

Phil Weldon wrote:
Thanks for posting the links. One question, however, about the
Anandtech review. Why does the writer think that a a micro-op is
only one byte long, and see the 64 KByte AMD instruction cache as
necessarily larger than the Intel 12 Kmicro-op cache? As far as I
know, the rest of the review may be spot on, but this item does make
me wonder.

The "average" x86 instruction is 2.5 bytes long (give or take), so a
12k-*instruction* cache would be approximately equavalent to a 32kbyte
cache. However, a lot of x86 instructions decode to multiple uops on the P4
(eg: those that access memory), which overall means that the trace cache is
equavalent to somewhere between an 8kb and 24kb instruction cache, depending
on the code that's being executed. Someone did some tests at some point
(slowly increased the size of a loop and plotted the results) which verified
this, but I can't find any results. If anyone has a P4 handy, I can quickly
whip up a program that would do it.

[...]

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Michael Brown
www.emboss.co.nz : OOS/RSI software and more
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"Wayne Youngman" wrote in message
...
Hi,

Reviews so far. . . .

Who needs a review? I've had one for over a fortnight. The architecture
might make sense once it hits the 4.5GHz or so area and there's software
around with SSE3 support, but right now, Northwood is a better bet IMVHO.
--


Richard Hopkins
Cardiff, Wales, United Kingdom
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In article , w
says...
If anyone has a P4 handy, I can quickly
whip up a program that would do it.

I have a P4... And i'd like to participate in your experiment, haha,
tell me what to do ;-)

Thomas

Sounds straight enough for me!

Ta.

Pete

"Richard Hopkins" wrote in message
...

"Wayne Youngman" wrote in message
...
Hi,

Reviews so far. . . .

Who needs a review? I've had one for over a fortnight. The architecture
might make sense once it hits the 4.5GHz or so area and there's software
around with SSE3 support, but right now, Northwood is a better bet IMVHO.
--


Richard Hopkins
Cardiff, Wales, United Kingdom
(replace .nospam with .com in reply address)

The UK's leading technology reseller www.dabs.com
Get the most out of your digital photos www.dabsxpose.com

Richard Hopkins wrote:

Who needs a review? I've had one for over a fortnight. The
architecture might make sense once it hits the 4.5GHz or so area and
there's software around with SSE3 support, but right now, Northwood
is a better bet IMVHO.

What really astonishes me is that they also release a 533MHz 2.8E Prescott
without HT. What's the point -- for machines that can't do faster than
133MHz bus speed, the Northwood 2.8 and 3.06HT are faster -- the latter
quite a bit faster, and at about the same price.
Unless SSE3 makes a *gargantuan* impact, I can't imagine any value
whatsoever in the more power-hungry and slower Prescott 2.8E.

Regards,
--
*Art

Thomas wrote:
In article ,
w says...
If anyone has a P4 handy, I can quickly
whip up a program that would do it.

I have a P4... And i'd like to participate in your experiment, haha,
tell me what to do ;-)

OK, the program (with some basic info on how to use it) is at
http://www.emboss.co.nz/downloads/ICB.zip
(264kb)

Delphi 7 source code included, though it's a bit of a hack job

--
Michael Brown
www.emboss.co.nz : OOS/RSI software and more
Add michael@ to emboss.co.nz - My inbox is always open