64 bit processors

On Tue, 14 Dec 2004 08:50:44 -0500, General Schvantzkoph wrote:

On Tue, 14 Dec 2004 09:26:40 +0000, Wes Newell wrote:

On Mon, 13 Dec 2004 23:52:45 -0500, General Schvantzkoph wrote:

64 bits refers to the address size not to data sizes,

Now that's a new one and I thought I'd heard them all.:-) Actually, this
is incorrect too though. The A64 address bus is 40bits, 48 virtual.

a 32 bit CPU can address 4 billion bytes

Tell me why my 32bit 68000 cpu can only address 16MB then (1 clue, it has
a 24bit address bus). I really haven't checked, but it's very possible to
have a 32bit cpu address more than 4GB. the amount of directly addressable
ram is controlled by the size of the address bus, and has nothing to do
with 32, 64, or 128 bit cpu's.

The physical address space of a CPU is almost never identical to the
virtual address. The virtual address space is what the programmer sees, so
in a 32 bit architecture that's 4G and in 64 bit architecture it's
1.6*10^19. The physical address space is determined by the width of the
Address Translation Unit RAM and the address pins on the CPU. The physical
address space is a choice that the CPU designers make for each design.
Pins and RAM cost money so you don't want to support a physical address
space that's larger than the maximum amount of RAM that the particular CPU
is ever likely to have. When the 68000 came out the biggest DRAM was 64K,
the CPU designers would have figured that at the end of life of the chip
the biggest DRAM would be the 1M DRAM so they picked 16M as the physical
address space because it was confortably larger then any real memory
system that it would ever have to support without being excessively
expensive. When you get to the end of an architecture's life, as we are
now with the 32 bit x86 architecture, it becomes possible to have more
real memory then virtual memory. The way this is handled is that CPUs can
support multiple virtual address spaces, each of which can have it's own
DRAM space. So a Xeon might have 16 separate threads each of which can
address 4G of RAM for a total of 64G of real memory. Each thread is still
limited to 4G but you can have lots of them. There are also ways to give
programmers access to more memory by using segmentation registers which
allows the programmers to manage multiple virtual memory spaces within one
process, that's what the 80286 did to extend the 16 bit address space of
the 8086. Segmentation is a horrible way to handle memory, a larger linear
address space is much easier for programmers to deal with. The AMD64
architecture is now back to where we were in the 68K days. The virtual
address space is so large that all the RAMs in the world couldn't fill it.
The programmer sees the 64 bit space but the actual amount of physical RAM
supported is much smaller, I'm not sure what the exact size is but I
suspect it's around 40 bits (1 terabyte) which would be confortably larger
than the amount of RAM that this generation of chips is likely to have to
support (assuming 4G and maybe even 16G RAMs by the time the last current
generation A64s are unplugged).

Aha, so now they consider the bitness of the cpu to be the maximum
possible address space within the architecture if you're sumize is
correct. I wonder who keeps changing the nomenclature. In the beginning it
was defined by the data bus size, then it changed to register size (I
think Intel was the first to do this, with the 8088). Motorola redefined
thier 16bit 68000 to calling it a 32bit later. And now we have a bitness
that virtually has nothing to do with anything speed wise, actual ram
address size or anything of any value. Next thing you know they'll be
adding up all the bus widths of the cpu and calling it an xxxx bit cpu.
Got to one up the competition.

--
Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB)
http://mysite.verizon.net/res0exft/cpu.htm

Think of it like this. 32 bit like taking a half gallon container and
filling a larger container,64 bit is taking a 1 gallon container and filling
the same larger container. the 1 gallon container will take less trips. DOUG

(Courseyauto) wrote in
:

Think of it like this. 32 bit like taking a half gallon
container and filling a larger container,64 bit is taking a 1 gallon
container and filling the same larger container. the 1 gallon
container will take less trips. DOUG

But it's heavier and will tire you out faster. You'll probably end up with
tendonitus, too.

(Courseyauto) wrote in
:

Think of it like this. 32 bit like taking a half gallon
container and filling a larger container,64 bit is taking a 1 gallon
container and filling the same larger container. the 1 gallon
container will take less trips. DOUG

But it's heavier and will tire you out faster. You'll probably end up with
tendonitus, too.

Not if the larger container is a gallon....

(Courseyauto) wrote in
:

(Courseyauto) wrote in
:

Think of it like this. 32 bit like taking a half gallon
container and filling a larger container,64 bit is taking a 1 gallon
container and filling the same larger container. the 1 gallon
container will take less trips. DOUG

But it's heavier and will tire you out faster. You'll probably end up
with tendonitus, too.

Not if the larger container is a gallon....

64-bits is more than a gallon, however. And even if it weren't, it's well
known that many computer users have Gilligan arms.

(Courseyauto) wrote in
:

(Courseyauto) wrote in
:

Think of it like this. 32 bit like taking a half gallon
container and filling a larger container,64 bit is taking a 1 gallon
container and filling the same larger container. the 1 gallon
container will take less trips. DOUG

But it's heavier and will tire you out faster. You'll probably end up
with tendonitus, too.

Not if the larger container is a gallon....

64-bits is more than a gallon, however. And even if it weren't, it's well
known that many computer users have Gilligan arms.

I know,they are 4 liters.

Aha, so now they consider the bitness of the cpu to be the maximum
possible address space within the architecture if you're sumize is
correct. I wonder who keeps changing the nomenclature. In the beginning
it was defined by the data bus size, then it changed to register size (I
think Intel was the first to do this, with the 8088). Motorola redefined
thier 16bit 68000 to calling it a 32bit later. And now we have a bitness
that virtually has nothing to do with anything speed wise, actual ram
address size or anything of any value. Next thing you know they'll be
adding up all the bus widths of the cpu and calling it an xxxx bit cpu.
Got to one up the competition.

It's always been the virtual address space that defined the bitness of a
CPU architecture. I've been in the business for 30 years and I spent the
first half of my career designing CPUs. Some marketing types in the
early days of microprocessors may have used bus size to define the bitness
of a microprocessor but no computer architect ever did that. The problem
with using register width or bus width is that it isn't consistant even
within a single CPU. The floating point registers in a 16 bit minicomputer
were 64 bits wide, that didn't make the computer a 64 bit computer. The
same thing goes for the memory datapath. The 939 pin Athlon 64s have two
64 bit memory buses, does that make them a 128 bit processor? of course
not. By the same token as serial buses like PCI express and SATA replace
parallel buses does that make the machines 1 bit processors? It is true
that the integer registers generally are the same width as the address
because you use the integer registers to compute addresses in most
architectures. However it's not required, you could use a pair of
registers to hold an address pointer. You can also have specialized
registers that are used only for addresses and other registers that are
used for general purpose integer arithmetic. In fact the base x86
architecture does use a god awful collection of single purpose registers
rather than a uniform general purpose register set.

Jerry G. wrote:

Very few
software's at this time are written in the 64 bit format.


Linux & some BDSs have been running 64 bit for years eg MIPS.
There are 64 bit builds of linux for Athlon 64.

gtoomey

On Tue, 14 Dec 2004 21:17:44 -0500, General Schvantzkoph wrote:


Aha, so now they consider the bitness of the cpu to be the maximum
possible address space within the architecture if you're sumize is
correct. I wonder who keeps changing the nomenclature. In the beginning
it was defined by the data bus size, then it changed to register size (I
think Intel was the first to do this, with the 8088). Motorola redefined
thier 16bit 68000 to calling it a 32bit later. And now we have a bitness
that virtually has nothing to do with anything speed wise, actual ram
address size or anything of any value. Next thing you know they'll be
adding up all the bus widths of the cpu and calling it an xxxx bit cpu.
Got to one up the competition.

It's always been the virtual address space that defined the bitness of a
CPU architecture.

Now this is s crock of the well known smelly subtance. :-)
So what's the virtual address space of the 16bit Motorola 68K cpu?
The real address bus is 24bits wide. The register size is 32bits, hence
the reason they redefined it as 32 bit after Intelalie started defining
there cpu's by register size. Look at some of your old data sheets from
both Motorola and Intel. Originally Intel defined the 8088 CPU as an 8 bit
cpu, which it was for all practical purposes. They later redefined as a
16bit CPU. Now that wasn't done by engineers. It was done by marketing.
Remember the old 80486SLC I think it was called. IIRC it had a fricking
8bit data bus and was as slow as crap flowing down a river ( from one
sucker that bought one) and Intel called it a 32bit cpu. Give me a break.
Tere's so much marketing BS floating around thee days one can't tell wtf
they're buying without a lot of in depth research.

I've been in the business for 30 years and I spent the
first half of my career designing CPUs.

And I started designing computer hardware in the late 70's after working
with them since about '71. Had to use a teletype to load the progam
with tape, but that really doesn't mean much today..

Some marketing types in the early days of microprocessors may have
used bus size to define the bitness of a microprocessor but no computer
architect ever did that.

I can't remember anyone ever using anything except the data bus width,
and I've got a good memory..

The problem with using register width or bus width is that it isn't
consistant even within a single CPU. The floating point registers in a
16 bit minicomputer were 64 bits wide, that didn't make the computer a
64 bit computer.

At the time, things were simple. there was no on board cache, so every
memory access had to go over the data bus. So the wider the bus the faster
the cpu. The problem of running 16bit instructions over an 8 bit data bus
should be obvious. Today, the bitness of the cpu has little impact on
performance as about 90% of all accesses ocur within the onboard cache and
all memory buses or at least as wide as the internal registers.


--
Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB)
http://mysite.verizon.net/res0exft/cpu.htm

Lieber Herr Schwantzkopf,


In fact the base x86
architecture does use a god awful collection of single purpose registers
rather than a uniform general purpose register set.

That has always puzzled me. Why in the heck did the micro designers take
that route?

(PS -- also thirty years in computer tech, started out, however, as a
mainframe maintenance tech, considerably lower than a CPU designer)