8800 gts too slow...

No One wrote:
citizen513 wrote:

Thank you good people,
I've found the problem.

I installed the card in second PCIe slot, on my DFi ultra-d board, and
the maual says it then runs at X2 instead X16 speed.
Checked with CPU-Z and really it is so.

So i have to move some jupers to enable 8X, at least untill I change
the pasive NB cooler that obstructs the card when in primary PCIe slot.

According to DFi forums, it improves perfs for about 20 %, exactly
what I was missing.

Thanks, SOLVED

I find all this wierd. From everything I read about PCI-express when it
came out (not to be confused with PCI-x and PCI-e), the "x factor" was
the slots width, not its speed. So, how does a mobo have a x16 width
slot with only x2 width pins?

That is the beauty of deception. You can use a big connector, like the
long one for PCI Express x16. But if the designer only wires two of the
lanes, the other 14 lanes are open circuit. The silicon is clever
enough to negotiate the "connection size", so the system eventually
figures out the slot is x1, x2, x4, x8, or x16 in size. Those
are all the potentially valid numbers of wired lanes.

Some motherboards have a really clever connector design, that also
takes advantage of this, but is less deceptive. Some motherboards
have a x4 sized connector, where the end plate is cut off the connector.
That allows an end user to plug a x16 card into an x4 slot, and the
unused pins of the 12 unwired lanes, sit in the air. At least with
that concept, an end user knows the slot can never deliver more than
x4, because there are only enough pins for x4.

(Yellow connector is a special, open ended design, and can take a x16 card)
http://www.hothardware.com/articleim...830/big_12.jpg

Note that "cheating" is not limited to "sub-connecting" the x16 sized
slots. There are also motherboards with x4 connectors, with only two
lanes wired.

If you want to check how a slot is wired, one trick is to "count
capacitors". Next to a PCI Express slot, the lanes are capacitively
coupled with tiny ceramic SMT caps. There is a pair of caps per lane,
and they'll be jammed next to one another. If a PCI Express x16 connector
is fully utilized, there will be at least 16 pairs of caps next to the slot.
This is how, on a recent deceptive motherboard offering, where a certain
6150 Nvidia derivative was offered for sale, it was possible to figure
out the product only had x8 worth of lanes. And in fact, that product
has been expunged from the Nvidia site. One day it was in their table
of chipset alternatives, and now it has magically disappeared.

So while the initial PCISIG standard may have expected an honest 1:1
relationship between "size of connector" and "number of wired lanes",
there are certainly a number of creative options.

SLI implementations add more fat to the fire. Using paddle cards, it
is possible to restrict available lanes. While the motherboard may have
the magic 16 pairs of caps, a paddle card can be used to disconnect
8 of them. But usually the accompanying motherboard documentation,
describes in some detail, that one position of the paddle card is
x16/x1 and the other is x8/x8. And don't ask me why they bothered
putting the x1 on there :-) One position of paddle needs 17 lanes
from the chipset, while the other uses 16 lanes.

Paul

If you want to check how a slot is wired, one trick is to "count
capacitors". Next to a PCI Express slot, the lanes are capacitively
coupled with tiny ceramic SMT caps. There is a pair of caps per lane,
and they'll be jammed next to one another. If a PCI Express x16 connector
is fully utilized, there will be at least 16 pairs of caps next to the slot.

Clever...
Thanks for the read, nice to know that stuff.

Paul wrote:
No One wrote:

citizen513 wrote:


Thank you good people,
I've found the problem.

I installed the card in second PCIe slot, on my DFi ultra-d board,
and the maual says it then runs at X2 instead X16 speed.
Checked with CPU-Z and really it is so.

So i have to move some jupers to enable 8X, at least untill I change
the pasive NB cooler that obstructs the card when in primary PCIe slot.

According to DFi forums, it improves perfs for about 20 %, exactly
what I was missing.

Thanks, SOLVED


I find all this wierd. From everything I read about PCI-express when
it came out (not to be confused with PCI-x and PCI-e), the "x factor"
was the slots width, not its speed. So, how does a mobo have a x16
width slot with only x2 width pins?


That is the beauty of deception. You can use a big connector, like the
long one for PCI Express x16. But if the designer only wires two of the
lanes, the other 14 lanes are open circuit. The silicon is clever
enough to negotiate the "connection size", so the system eventually
figures out the slot is x1, x2, x4, x8, or x16 in size. Those
are all the potentially valid numbers of wired lanes.

Some motherboards have a really clever connector design, that also
takes advantage of this, but is less deceptive. Some motherboards
have a x4 sized connector, where the end plate is cut off the connector.
That allows an end user to plug a x16 card into an x4 slot, and the
unused pins of the 12 unwired lanes, sit in the air. At least with
that concept, an end user knows the slot can never deliver more than
x4, because there are only enough pins for x4.

(Yellow connector is a special, open ended design, and can take a x16 card)
http://www.hothardware.com/articleim...830/big_12.jpg

Note that "cheating" is not limited to "sub-connecting" the x16 sized
slots. There are also motherboards with x4 connectors, with only two
lanes wired.

If you want to check how a slot is wired, one trick is to "count
capacitors". Next to a PCI Express slot, the lanes are capacitively
coupled with tiny ceramic SMT caps. There is a pair of caps per lane,
and they'll be jammed next to one another. If a PCI Express x16 connector
is fully utilized, there will be at least 16 pairs of caps next to the
slot.
This is how, on a recent deceptive motherboard offering, where a certain
6150 Nvidia derivative was offered for sale, it was possible to figure
out the product only had x8 worth of lanes. And in fact, that product
has been expunged from the Nvidia site. One day it was in their table
of chipset alternatives, and now it has magically disappeared.

So while the initial PCISIG standard may have expected an honest 1:1
relationship between "size of connector" and "number of wired lanes",
there are certainly a number of creative options.

SLI implementations add more fat to the fire. Using paddle cards, it
is possible to restrict available lanes. While the motherboard may have
the magic 16 pairs of caps, a paddle card can be used to disconnect
8 of them. But usually the accompanying motherboard documentation,
describes in some detail, that one position of the paddle card is
x16/x1 and the other is x8/x8. And don't ask me why they bothered
putting the x1 on there :-) One position of paddle needs 17 lanes
from the chipset, while the other uses 16 lanes.

Paul

So, my memory hasn't failed me, it IS width and not speed.

No One wrote:


So, my memory hasn't failed me, it IS width and not speed.

Each lane is 250MB/sec. If you have x2, then 500MB/sec is available.
If x4, then 1GB/sec is available. (And those numbers are full duplex,
since there are TX and RX wires on each lane. AGP was half duplex, and
you could transmit or receive, but not both at the same time.)

The lanes basically work in parallel, to increase the available bandwidth.
So it is effectively speed.

To compare to AGP for a moment. AGP had a fixed bus width. The number of
wires was the same all the time. To move more data, they increased the
effective clock rate on the bus.

PCI Express is different, in the sense that a lane is fixed in performance.
It is 250MB/sec. But the lanes can be used in parallel, so two lanes
carries twice the megabytes/sec of one lane. So in that sense, width is speed.

Note that there is a new offering coming soon. PCI Express 2.0 will offer
a wire running at twice the speed. I believe, like all good bus standards,
it is backward compatible, and a well designed 2.0 product should work
with a 1.0 product. It would just drop back to the originally designed
transfer rate. (Almost like how the two SATA rates work for people.)
So you should see more announcements of motherboards or video cards with
even more effective bandwidth to offer. It remains to be seen whether video
cards really need this. (Looking forward to seeing benchmarks when they become
available.)

If a video card slot offers 8GB/sec, the question will be whether the
memory controller on the motherboard, can actually sustain that kind of
rate. It could be, that the early attempts to do this kind of
stuff, fall short of running at the full rate. Which is why the early
benchmarks should be interesting. It may take years to fully take
advantage of the new standard.

Paul