Robert Redelmeier wrote:

In comp.sys.ibm.pc.hardware.chips Robert Myers wrote:

The 6mb cache is an act of desperation on Intel's part. I don't


Agreed. yet ...


_think_ their strategy is to keep increasing cache size. It's a
losing strategy, anyway, unless you go to COMA. Itanium's in-order
architecture is just too inflexible, and the problem is still cache
misses.


Then how do you explain the _dismal_ performance of the
Celeron4 with only 128 KB L2 and poor showing of the first
P4 with 256 versus the current P4 at 512 KB? These are
all the same P7 core with the same small L1s.

I can't blame Intel for wanting to try more cache.
This is obviously a game of diminishing returns, and the
P4EE seems to be past. 512 KB seems optimal for current
datasets/problems/benchmarques. Cache MATTERS.

The non-Intel crowd has known that for years. But cache is
also expensive.


Notice also how the AMD K7 improved from 256 to 512.
The Duron, with the tiny 64 KB L2 performs amazingly well.
Decent L1s and the excellent organization of L2 (16 way,
exclusive) saves it from the Celeron4's fate.

-- Robert



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After being targeted with gigabytes of trash by the "SWEN" worm, I have
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