View Single Post
  #2  
Old November 29th 11, 09:33 PM posted to alt.comp.hardware.overclocking.amd,comp.sys.ibm.pc.hardware.chips
Paul
external usenet poster
 
Posts: 13,364
Default BIOS voltage terminology?

Yousuf Khan wrote:
What are the following terminologies:

(1) CPU Over Voltage (aka Vcore)?
(2) VDDNB Over Voltage?
(3) Loadline Calibration?

Yousuf Khan


(1) CPU Over Voltage (aka Vcore)?

"Over Voltage" means being able to offset the VCore voltage,
so it is higher than the range suggested by the CPU manufacturer.
Normally, the VID codes coming from the processor, are range
limited, to suit the CPU manufacturer and the amount of
"field returns" they can expect for "defective processors".
Range limiting VID, is supposed to prevent people from
abusing their processors.

An enthusiast board, can add an analog offset to the
regulator voltage, in an attempt to thwart the
digital (VID value) limitations imposed by the CPU manufacturer.

VCore = [dig VID low .. dig VID high] + analog_offset

VID changes "on the fly", to support EIST or Cool N' Quiet.
So the digital value, doesn't stand still. It changes while
the computer is running, as a function of P-State desired.
Disabling EIST or CNQ, should make VID a constant value.

If your board doesn't support Over Voltage (like my very nice
$65 Asrock motherboard), you can add a resistor or do a "pencil
mod", to do the offsetting yourself. I added 0.1V to VCore,
by adding a resistor to the regulator. The regulator had
a trim point, making the addition of the resistor easy.
All you need for hints, for home hacking, is the regulator
datasheet.

The regulator has an internal check, which will turn off the
regulator if you go too far. The regulator checks for MOSFET
failures, by monitoring the output voltage. If a design tries
to "trim too high", the regulator will assume a MOSFET has
failed short, and will turn off MOSFET drive signals in response.
Or, attempt to clamp the voltage, by turning on all the low side
MOSFETs until something burns or blows. All in the name of
protecting an expensive CPU from damage.

(2) VDDNB Over Voltage?

AMD processors now, have Integrated Memory Controllers
right on the processor die. A recent change to the CPU
designs, is the move to split plane powering. When you
buy a motherboard with "4+1" phases, the four phases are
for Vcore, while the fifth phase powers VddNB.

I couldn't find any nice pictures, with all the voltage shown,
so this will have to do. There are actually many voltages
in a motherboard design, but I need a nice picture to list
them all.

http://images.ht4u.net/reviews/2011/...sorgung_th.png

(3) Loadline Calibration?

There is a picture of the datasheet specification here. This
shows a loadline graph, and Intel's spec for "acceptable behavior".
So if your VID was putting out a fixed value, this graph
shows how the voltage as measured at the silicon die, changes
as a function of the current drawn by the processor. Processor
current, goes up in proportion to computing load.

http://support.asus.com/Search/KDeta...44C32C8400&t=2

That's a curve of VCore versus ICore. Core current flow increases,
when you run Prime95. The operating point shifts to the right.
The processor draws 100 amps of current.

If I stop running Prime95, and go back to idle, the processor
draws 20 amps. Some of that could be DC leakage for example,
and not contributing to getting anything done.

If you had a hardware monitor running at the time, and you
were an enthusiast, you'd look at that and say "oh, my,
look at that voltage droop". The change from 20 amps to 100 amps
of draw, could result in an observed 0.15V change in measured VCore
value.

Loadline calibration, is an attempt to make the enthusiast
feel better. It "flattens" out the line, so it's no longer
a diagonal, but instead shows little voltage change with
load current (a horizontal line). Doing so, likely violates
the rules shown in that graph. The question I can't answer,
is whether enabling a feature like that, is actually helping
matters. In some ways, it's like a VCore shift.

That load line has always bothered me. With closed loop
feedback and remote sensing, you can null out a lot of
that behavior. So when Intel draws that graph and says
"thou shalt make it this way", I have to wonder why. I've
never seen an explanation in plain English, why it has to
be that way. In the usual way, Intel draws that graph,
without even one stinking comment about "why".

Paul