On Wed, 26 Oct 2005 08:17:17 -0700, YKhan wrote:

No real details here, just a "stay tuned" message, but that should be
enough to start wild speculations running.

"One strategic path that will knock you for a loop, and which I'll
detail soon, is AMD's coming escape from the confines of Intel's
x86 instruction set. To this point, AMD has resisted the temptation to
overhaul the x86, even though it sorely needs it. When Fab 36 cranks
up, AMD will overcome that fear. AMD64 processors will take on
performance, scalability, resource management, and availability-related
instruction set extensions that will be proprietary to AMD CPUs.
Don't freak out: AMD will keep its contract to be 100 percent
compatible with Intel-standard processors. But the idea of seeing
"optimized for AMD64" stamped on software boxes delights me. "
http://www.infoworld.com/article/05/...rss&url=http:/
/www.infoworld.com/article/05/10/26/44OPcurve_1.html

or, http://tinyurl.com/cvvwn


A sharp barb the subject "AMD to leave x86 behind?" is.
Very good.
A rising star among us trolls Khan is becoming.


I'll start off with my own wild speculation. There was word that prior
to choosing SSE2/SSE3 as its AMD64 floating point instruction set, AMD
was investigating going its own way. So I'm going to speculate that AMD
will extend floating point out with its previously abandonned
instruction set. I'm going to speculate that this instruction set will
be a full scientific functions instruction set, just like the old x87
FPU was, except without the stack-based register system. And let's say
it'll have 32 FP registers instead of just 16 like SSE does.

Yousuf Khan


SIMD FP is a bad idea. Think of it as CISC FP.

Dunno about AMD's SSE implementation.
But Intel P6 treats SIMD FP as CISC FP in some sense.
P6 decomposes a 4-way PADD into two 2-way PADDs
and sends the pair down Port 0 and 1
(or sequentially to one port if the other is busy).

Most 3D apps calculate (X,Y,Z) rather than (X,Y,Z,W).
So a FPU with 3 pipes, not 4, is more appropriate.
And don't tell me I must "swizzle" my vertex arrays.