On Wed, 29 Oct 2003 20:07:47 -0800, Scott wrote:

On Tue, 28 Oct 2003 14:23:18 -0800, Malcolm Weir
wrote:

So what? I'd certainly *hope* that the embedded CPU isn't touching
the data at all...
Actually most of the systems use the CPU for parity calcs

*delicate shudder*

We had a soft-programmable DMA-engine FPGA doing this in 1994, maybe
95. It had a simple "language" which we encoded as the least
significant bits of an address to process. The commands we

LOAD
XOR in data
SAVE
HALT/INTERRUPT

One just pointed the thing at a list of memory addresses and let it
get on with it.

* newer chipsets have the appropriate asic on board which works much
faster

What "appropriate asic"? Works much faster than *what*?

The LSI controller (also used by StorageTek's Bladestore ATA offering)
uses a dedicated ASIC for this, freeing up the CPU to only do traffic
control and config.

As I'd expect! Although an ASIC is a refinement (over the FPGA).

A problem with (oddly enough) more advanced processors doing XOR work
is that you have to flush the processor's data cache and pipeline in
order to permit the IO processor (the SCSI controller) to access the
updated data...

(The standard multiprocessor cache coherency problem)

Scott

Malc.