On Tue, 25 Oct 2005 17:37:08 -0400, daytripper wrote:

On 25 Oct 2005 12:00:45 -0700, "YKhan" wrote:

EdG wrote:
Wasn't Intel talking about using a high-speed interconnect a long time
ago, maybe a year or two before Opteron? GIO or something? What happened
with that?

Yeah, that was 3GIO, which became Arapahoe, which became PCI-Express.
That was in a futile attempt to derail any momentum building for AMD's
Hypertransport. Of course PCI-E is no competition for HT, it's much too
bloated to be a chip-to-chip interconnect. AMD never fell for it, and
kept HT as simple as possible while Intel threw as much bling-bling
into PCI-e to dazzle people with features.

Now it looks like AMD might even use PCI-e against Intel, if the
rumours about AMD building a PCI-e link directly into its processors
can be believed.

And not long ago I read somewhere Intel was going to use a dual bus like
the one AMD used on the Athlon MP, I can only hope that was false or
they have now dumped that too, I doubt it would get them far, still a
shared bus right?

Yeah, I think that was supposed to be in the Deerfield processor that
Intel just cancelled.

Yousuf Khan

The whole fleet of next years Xeons (now heating up verification labs at
select OEMs) use a separate hose for each processor to MCH connection. They're
not going to get to 1333mhz fsb speeds with daisy-chains...

Ok, but am I the only one who detects Intel trying to defend the
indefensable? IBM tried to hold the "upper ground" too, oh, about 15
years ago. ...and had a better position (different ISA).

--
Keith