On Mon, 24 Oct 2005 21:06:39 -0500, EdG wrote:

On Mon, 24 Oct 2005 20:01:21 -0400, Yousuf Khan wrote:

Tigerton, get used to that name. Apparently it's gonna have
Hypertransport in it. :-)

Intel Shifts Plans for Server Chips: Financial News - Yahoo! Finance
http://biz.yahoo.com/ap/051024/intel...hips.html?.v=2

PS- oh, and it's also delaying the Montecito Itanium, as EdG posted.

Yousuf Khan

Wasn't Intel talking about using a high-speed interconnect a long time
ago, maybe a year or two before Opteron? GIO or something? What happened
with that?

Well there was NGIO and then 3GIO, which became PCI Express.

IIRC 2007 is the scheduled intro of the common Intanium/x86 bus, which is
expected to be an integrated memory controller architecture a packetized
I/O bus -- CSI or sumthin'??.

And not long ago I read somewhere Intel was going to use a dual bus like
the one AMD used on the Athlon MP, I can only hope that was false or
they have now dumped that too, I doubt it would get them far, still a
shared bus right?

I believe the dual independent bus is scheduled for next year some time
with the new 65nm & P-M derived desktop/server chips... dunno if that's
what Bensley is supposed to be. All those damned code names drive me nuts.

--
Rgds, George Macdonald