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Old April 9th 04, 01:58 AM
David Maynard
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P2B wrote:



David Maynard wrote:

BigBadger wrote:

No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333 is
just
AMD hype to sell the virtues of the DDR bus. Intel do the same trick but
they multiply the real bus speed by 4x.




Double and quad pumping the bus is not "hype." It's an engineering
technique for transferring data twice, or 4 times for quad, per clock
cycle.

333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
number from a performance standpoint.



I don't see much point in arguing this one in technical terms.

The fact is the term 'FSB' was used for many years to refer to the
memory/processor bus *clock frequency*,


The term "FSB" has always referred to the "Front Side Bus" and not a
'clock'. What you refer to is simply that, for a considerable length of
time, the Front Side Bus 'speed', I.E. data rate, was coincident with the
base rate of the system clock.

It isn't, however, when the bus is dual or quad pumped.


and reusing the same term for
the bus *bit rate* has caused no end of confusion and was therefore a
Bad Idea (tm).


I'm not using the term "FSB" to refer to a 'clock' or 'bit rate' or
anything other than what it's always referred to: the "Front Side Bus."


One could also argue that use of the term 'hertz' (as in MHz) in
reference to anything other than the periodic interval of a waveform is
incorrect. Heinrich Rudolf is probably spinning in his grave :-)


Yes. In previous discussions I've also pointed out that same argument as
the perspective of the 'purist'. It does, however, beg the question about
the data rate of a 166.6Mhz clocked double data rate bus being 333 'what'?
To which I mused perhaps we should regret having changed from the original
designation of "Cycles/Second" to "Hertz." (It's interesting to note that
few would find such a problem with a bus rate designation of 333
'Mega-Cycles/Second' but do when the synonym "Hertz" is substituted)

"MHz" may not be a 'purist' form of usage here but it captures the
pertinent aspect of the bus speed in a context consistent with the single
data rate bus and is certainly not 'hype', which was the original point.

I.E. Of what relevance to the 'real' (sic) 'bus speed' is it how the
designer derived his timing signals? Other than to 'techies', that is.