Michael Brown wrote:
David Maynard wrote:

BigBadger wrote:


No it's not 333MHz, it's actually a 166 'MHz' FSB processor....333
is just AMD hype to sell the virtues of the DDR bus. Intel do the
same trick but they multiply the real bus speed by 4x.

Double and quad pumping the bus is not "hype." It's an engineering
technique for transferring data twice, or 4 times for quad, per clock
cycle.

333 is the bus cycle rate, e.g. "Bus Speed," and is the relevant
number from a performance standpoint.


Oh dear, oh dear, here we go again ... It depends on whether you measure
the control lines or the data lines for quoting the "bus speed" number.

No it doesn't. It has to do with how many data transfer cycles there are.

I actually think a more accurate way of representing it (performance-wise)
is a 128-bit bus (DDR) or 256-bit bus (QDR), both running at 166MHz.

Except it isn't '128 bits' or '256 bits' wide. It does, however, transfer
data at either 2, for dual pumped, or 4 times, for quad pumped, the system
clock rate.

A good
example is the latency for main memory.

Which is a separate component independent of the bus and not even ON, or
even necessarily run at the speed of, the bus at issue.

Say you have a 166MHz DDR system
(aka DDR333), and a 100MHz QDR system (aka QDR400), and the CPU runs at 1GHz
(6.0x for DDR, 10.0x for QDR). Excluding memory latencies, to fill a
randomly-accessed 64-byte cache line would take:
Waiting for bus strobe: 3.0 cycles (DDR system), 5.0 cycles (QDR system)
Transferring data: 24 cycles (DDR), 20 cycles (QDR)
Total: 27 cycles (DDR), 25 cycles (QDR)

So DDR333 is, under random access conditions, only marginally slower than
QDR400. The actual break-even point is 180MHz (actually slightly above due
to memory latencies), but hopefully you get the idea. Of course, the QDR
system will perform better under "streaming" type conditions, where the
higher latency won't matter so much.

No, you're analyzing the memory, not the processor bus.

We can sit here all day long proposing new terminology but that's
irrelevant to the matter.


Incidentally, this issue is exasparated by the P4's 128-byte cache line, as
opposed to the 64-byte cache line of the K7.

Processor (L2) cache has nothing to do with bus speed. It affects processor
performance, of course, but then so does the L1 cache, cpu architecture,
and core speed: none of which have anything to do with the bus speed either.

Btw, what don't you call a 3.4 Gig P4 a 200Mhz P4 because the 'real clock'
(sic) is 200 Mhz. That 3.4 Gig number is just 'hype'.

Finally, using the non-multiplied speed would stop people complaining that
their motherboard only goes up to 250MHz

Requiring everyone to use the same bus and speed would solve it too but
that hardly means it's desirable.


[...]

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Michael Brown
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