On Wed, 01 Oct 2003 06:51:23 +0000, Tony Hill wrote:
Measuring a bus by it's data rate is in no way marketing, it's the only
worthwhile way to measure a bus!
It is when the bus speed is 200MHz DDR or QDR but you call it 400MHz or
800MHz, when it isn't.
Would you prefer a P4 bus that
is "somewhere in the 70 to 350 clock cycle range" description? How does
that even begin to remotely help anyone?!
I prefer that when they talk about bus speeds that they follow excepted
practices and give the real speed. I can determine the the data rate from
that. A simple 200MHz DDR or 200MHz QDR would be fine.
Most even semi-remotely technical info about processor specs lists both
the clock speed of the bus and the bandwidth, and that's for desktop
processors. The clock speed (or at least effective clock speed with
today's double and quad data rate buses)
Both the P4 and Athlon now have a 200MHz FSB. Anything higher than that is
overclocked. There's no 400MHz FSB and no 800MHz fsb. Effective? Compared
to what? The P4 isn't an effective fsb of 800MHz if you compare it to the
Athlon FSB now is it? It's only effective 400MHz. Just another reason the
effective arguement is BS unless it's fully explained what it's compared
to. Yeah, I know, you know, but believe me, 90% of the people don't. And
that's why it's marketing BS.
has been ok for
the PC world since we've had 64-bit buses on every system for nearly 10
years now.
10 years? It only started with the Athlon and P4. Prior to that all x86
cpu's had only one data bit per clock cycle.
So the Pentium was a 64-bit processor, as are all current PC chips
So if the P4 is a 64bit cpu, why won't it run a 64bit OS?
except for the Athlon64, which is now a... umm.. what do you call the
Athlon64 which doesn't have a data bus? A 0-bit processor? Or
perhaps it's a dual-processor 16-bit unidirectional chip because it
has two 16-bit unidirectional hypertransport links? What the heck
does that make the Opteron then?
To be honest, I haven't looked at the architecture that much. From what
I can tell, the data comes across the HTL, which is 72 bits wide.
Umm, huh? HTL = Hypertransport Link? If so, it's 32-bits wide, 16-bits
in each direction.
with the
Opteron/64FX having 2 of them for 144bits. Thus the much improved
throughput of data to the core, and also why the regular A64 is quite a
bit slower than the FX/Opteron series.
I think you're confusing it's integrated memory controller with the
hypertransport link. Which is your "data bus"? At best this is only
slightly confusing in a single processor system, where you have memory
requests coming over one bus and all other I/O going over a single
hypertransport link. On multiprocessor systems, this gets MUCH worse,
as your memory could be local (going over your own memory bus) or remote
(going over a hypertransport link).
You're right. It's the data bus that's 72bits wide on the A64, and 144bits
on the Opteron/FX. Don't know what i was thinking.
Face it, defining the bit-ness of a chip by the width of the data bus
makes absolutely NO sense at all in this day and age! The Athlon64 and
Opteron are 64-bit chips because:
1. They have 64-bit integer registers 2. They use 64-bit address
pointers and address registers, program counter, etc.
So why does the Opteron/FX cpu's blow away the A64's at the same clock
speed if the data bus doesn't mean anything? That's the only difference
between them.
--
Abit KT7-Raid (KT133) Tbred B core CPU @2400MHz (24x100FSB)
http://mysite.verizon.net/res0exft/cpu.html