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Old January 13th 12, 05:47 PM posted to comp.lang.forth,comp.sys.intel,comp.arch
Joe keane
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Default Can someone explain step by step how one avoid many conditionalin forth as described in Moore Fourth essay?

In article ,
Andy (Super) Glew wrote:
I believe an IBM chip did eager ifetch - fetching both sides of a
branch - but did not actually execute, stalled at decoder or
therabouts.


Doing some 'early' loads seems like a good idea, assuming that you have
some IF units free.

But that is a *lot* different from the other suggestion, copying the
machine state to a different core.