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Old January 11th 12, 12:29 PM posted to comp.lang.forth,comp.sys.intel,comp.arch
Alex McDonald[_2_]
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Default Can someone explain step by step how one avoid many conditionalin forth as described in Moore Fourth essay?

On Jan 11, 12:21*pm, "Rod Pemberton"
wrote:
"Arnold Doray" wrote in message

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[Forth code]


CPU pipelining is improved by reducing conditionals. Modern CPUs have
branch prediction, but these aren't always successful, in which case the
pipline needs to be flushed, lowering the CPU's throughput.


Is that still true for multiple cores?

I.e., I would think the following is entirely possible and plausible, but I
haven't studied a CPU design in decades. *The CPU's designers could execute
the process in parallel with one core taking one direction for the branch
and the another core taking the other branch direction. *Once the correct
branch is determined, the bad execution path is discarded. *If the primary
core had the good execution path, it just continues execution. *If the
alternate core had the good execution path, it's internal state could be
"pushed" to the primary core. *If they used static ram for the internal
state, then it could be "pushed" asynchronously, i.e., between clocks or
sub-clocks. *It would require reserving a core for the branch path
execution, at least temporarily.

Rod Pemberton


Search on "speculative execution". It can also be done at the compiler
level; that doesn't require processor support. Intel's P6 was their
first chip to support it iirc.