James Hanley wrote:

David Maynard wrote in message ...

James Hanley wrote:

David Maynard wrote in message ...


James Hanley wrote:



snip

Just how fast do you think it can get instructions to execute if you turned
the FSB down to 1 Hz, eh?
It doesn't make any difference how fast the CPU can execute instructions if
you can't feed it the instructions to execute.


I was wrong on that one. thanks for your response


and the RAM multiplies the FSB.

No. It doesn't 'multiply' the FSB. It operates at the memory bus clock rate.


Ok. The thing that made me think it multiplied the FSB was
a)If my memory serves me correctly, Si Sandra lists alongside the
actual and effective memory clock speeds, a multiple, which seems to
work out the actual memory speed correctly if taken as a multiple of
the actual fsb speed.
b)the FSB is often called the base clock, since - i've been told - all
clocks in the system are derived from it - thus, I thought maybe the
memory clock speed was derived from it too (with a multiplier).

Well, more like 'system clock' but it, itself, is 'multiplied' from a lower
clock.

The point I was making is that there is no 'multiplier' *in* memory sticks,
as there is with the processor. Memory simply runs at the speed of the bus
it's on.

Typically the memory bus operated at the same speed as the FSB but modern
northbridge implementations often allow for running it at some 'ratio' to
the FSB. That 'not the same as FSB' memory bus clock is generated by the
northbridge and it's not a 'memory' clock, as in the sense of the CPU, it's
a memory *bus* clock.

"Multiplier" has multiple (pun) meanings. One refers to a mathematical
relationship. I.E. 266 is 2 times 133. The other refers to how that number
is physically implemented in the hardware.

While DDR is 'x2' SDR, in terms of theoretical bandwidth, it is not done by
'multiplying' a 133 Mhz clock to get a 266 Mhz clock. It is accomplished by
sending data on both the leading and trailing edges of the same, as SDR, clock.

I.E. | 1 cycle |
____ ____
| | | |
clock --- ---- ---

| | | |
SDR Data | Data |
| | | |
DDR Data Data Data Data

The clock speed is the same and there is no 'multiplier' creating a new,
'double speed' clock. Yet the effective speed is '2x' because it sends the
data twice per clock.

The CPU *does* have a 'multiplier'.

I.E. __________________Processor Package_______________
| |
System | |
clock -- CPU pin -- phase lock loop -- internal CPU clock |
| ^ |
| | |
| multiplier |
|_________________________________________________ _|

The internal CPU clock operates at xMultiplier the external clock.


I can accept that si sandra is being misleading and that the clock is
independent, since the BIOS does not have a setting to change any
'memory multiplier'.

I'm not sure what 'significance' you're trying to ascribe to 'derived' vs
'independent'.


Maybe the thing I had been told that "all clocks in the system are
derived from the base clock - fsb clock" is wrong, and should read
"all clocks in the system are synchronized with the base/fsb clock"

It's an oversimplification that ignores what part of the system is doing
what and why.

So the FSB has its own clock, the Synchronous Memory has its own
clock.

It's both 'their own clock' and derived.

But the PCI, AGP and CPU have a derived clock? (I make this
statement by looking at where in the bios i can set the multiplier)



thanks