http://forum.beyond3d.com/showthread.php?t=40661

quote 'one':

"As announced a month ago, yesterday At Cool Chips X, IBM did a
presentation about the SPE in the new 65nm Cell B.E. for HPC with DP
enhancement. Tech-on has an article (reg required).

The Enhanced BE supports DDR2 (DDR2-800) up to 16GB. The DP FLOPS
increased from 25.6 Gflops to 102 Gflops, the DP latency is reduced
from 13 cycles to 9 cycles with a full pipeline and dual issue. It
supports denormal and expected NaN to be more IEEE compliant. Its SPU
ISA is v1.2, with 5 new DP instructions. The transistor count is 250
million (from 241 million for 90nm Cell), the chip area is 212 mm2
(from 235 mm2), and it consumes 100 watts (from 110 watts).."

http://techon.nikkeibp.co.jp/article...5/P1030856.jpg
http://techon.nikkeibp.co.jp/article...5/P1030852.jpg