On Sun, 24 Oct 2004 09:41:42 -0400, keith wrote:

And the square of the voltage. Note that the voltage may have to be
cranked up to get more GHz.

Sure, and don't forget voltage. Leakage curent rises with something like
the square of the voltage (maybe even more), so static power rises by the
third power.

So both the dynamic power and static power rises exponentially to the
voltage applied? Thus if I take a 3Ghz Prescott, changes the voltage
from say 1.4V to 1.5V and measure an increase of 5W power while idle,
this would imply that the increase in leakage current is 500A!?? Since
the current increases with the square, so 5W = 0.1*0.1 * A therefore 5
/ 0.01 = A = 500A? At cube, it becomes even crazier

Ok, I did that before I saw the formula you gave later as (VDD1/VDD2),
thus is it (1.4/1.5)^3 * A = 5, hence A= 6.15 which sounds a WHOLE lot
more credible. Would this also mean that the actual leakage can be
1.5V x 6.15A = 9W or would it be 1.5V x (6.15A + X) where X was the
original leakage current at 1.4V?

Please don't laugh too hard if the maths is hopelessly naive & wrong
PPPP


What they're pointing out is that when one reduces the design-point
Vdd, one must compensate by reducing the threshold voltage of the devices
(Vt must be less than Vdd or the gate won't switch). Lower Vt devices have
a sub-threshold leakage far worse than higher Vt devices. A particular
device doesn't leak more at lower voltages, rather it's a side-effect of
the choice (need) to go to a lower Vt device.

Hmm, I'm getting a little confused (as usual). Maybe it's because I
don't truly understand what's Vdd and Vt. Am I correct to understand
that Vdd is what's commonly known as VCore, i.e 1.4V for the Prescott,
while Vtt is some internal design parameter that we will not know, e.g
1.3V for the Prescott. Therefore if they attempted to drop the VCore
to say 1.2V and therefore drop the internal Vt to say 1.1V to
compensate, the leakage problem will increase even though the voltages
had dropped?

How would this play out with the decrease in leakage current since
voltage dropped and leakage responds exponentially to that? Can it be
said that theoretically it can be designed so that the decrease in
leakage from the voltage drop cancels out the increase in sub
threshold leakage so that using a lower Vdd/Vt won't hurt in terms of
leakage current and therefore help lower the total power dissipation
since dynamic power will be drastically reduced with lower VCore/Vdd?

Would this Vt/Vdd issue be also the reason for the popular practise of
raising VCore to get higher clockspeeds for the overclockers. Since
it's been mentioned higher voltages help transistors switch faster.
i.e. the transistors cannot switch faster at the default Vt say 1V and
in order to do say 4Ghz, it needs to up Vt to say 1.35V and at the
default VCore of 1.4V, the difference isn't big enough to allow this.
Hnece raising VCore to 1.5V then allows the overclocker to overcome
the designed Vdd/Vt limits?

Exactly. If you want to measure leakage power, shut the processor clocks
off (put the processor to sleep).

Is this the same as the normal idling mode or would it be a special
function that can be enabled by software i.e. sending a particular
instruction to the processor and see the PC stop responding? Or would
we get a good approximation by compiling a small asm program running
in DOS (or maybe some bare minimum linux kernel to minimize OS
interference) that does nothing except endless loop of HLT? Since
googling about this imply that HLT only puts the processor to sleep
until the next interrupt. This would be relatively often due to the
real time clock interrupt isn't it?

If you vary clock speed only, the Y-intercept (clock = 0) point would
indicate the leakage. At least at this level, forget "short" and
"static" power terms and include "static" and "leakage" in the static
term, and "dynamic" and "short" in the dynamic term:
Total = dynamic + static

Thanks for making it simpler & clearer!!! *hugz*

Now to figure out a way to make it clock=0 so that I can sate my
curiousity :PpPpP

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