On Sun, 24 Oct 2004 07:16:24 +0000, The little lost angel wrote:

I know I'm a bit slow to start looking up this since the Prescott
thrust the issue into lime light. I didn't quite follow the major
discussion some weeks back. My friend got himself a spanking new
Prescott and claims it wasn't that hot despite claims. Yet Intel did
cancel the 4Ghz version so it got me thinking again whether the heat
increases dramatically with clockspeed. Since leakage was the big
thing thrown about, whether that was what increased with clockspeed.
And whether we could do any experiments to test it out.

So I started doing some reading up mainly from the tutorial document
posted some time back. Tried to understand these issues but don't
think I got very far. Would appreciate it greatly if the resident
experts here point out where I might have understood it wrongly.

You likely didn't. ;-)

I don't understand most of the explanations for how these are
calculated (most of the documents assume proficiency with mathematical
symbology which every regular visitor here knows by now I suck at
PPpP). So here's my best effort at arriving at something useful to
me as a layperson who's interested only in getting a useful real world
approximation of how these things are, say x.x rather than x.xxxxxx
kind of accuracy PpP

Reading, googling and all that, I get formulas and statement that
generally say that

Total Power = Dynamic Power + Static + Leakage + Short Circuit

You're author uses some pretty strange terminology, but it's really
somewhat simpler (and more complicated than that. Very little in a
processor these days is what a your author would call "static". The
PLL would have its static aspects, and likely nothing else. The term
"static power" is considered to be "leakage".

"Short circuit" current, I've always heard called "shoot-through" and
lumped in with dynamic power, so your equation drops to two terms;
Dynamic and Static. ...not that these other things don't exist, they just
aren't that interesting to anyone other than the circuit designer.

Dynamic power is directly related to clockspeed.

And the square of the voltage. Note that the voltage may have to be
cranked up to get more GHz.

Leakage doesn't care
about clockspeed and is a function of the process/technology but appears
to be in direct relation with temperature, i.e. hotter processors will
leak even more power?.

Sure, and don't forget voltage. Leakage curent rises with something like
the square of the voltage (maybe even more), so static power rises by the
third power.

I got a bit confused with a graph that displaying Leakage current vs
Vgs. http://www.cse.psu.edu/~vijay/iscatu...al-sources.pdf at
pg 7. It seems to imply that lowering voltages will increase the
leakage??

What they're pointing out is that when one reduces the design-point
Vdd, one must compensate by reducing the threshold voltage of the devices
(Vt must be less than Vdd or the gate won't switch). Lower Vt devices have
a sub-threshold leakage far worse than higher Vt devices. A particular
device doesn't leak more at lower voltages, rather it's a side-effect of
the choice (need) to go to a lower Vt device.

Anyway, the point is, can I say that given the usual x86 processor. The
difference between the power dissipated at 3Ghz and at 4Ghz is still
mostly clockspeed.

No, one makes certain design/processing choices to enable 4GHz. These
choices lead to higher power dissipation. If you took your 4GHz device
and ran it at 3GHz, and at the same voltage, then the dynamic power
difference would be simply the "clock speed" (i.e. 3/4 dynamic power), but
still the full static/leakage power. You wouldn't have reduced the total
power by 3/4. Of course you don't need the full Vdd at reduced frequency,
so you may be able to reduce that, which will lower the dynamic power
further (by the square of Vdd1/Vdd2) and static power (by perhaps the
cube).

Because dynamic power has to do with whether there's any actual
activity, both a 3Ghz and 4Ghz would have similar power draw when idling
since leakage will be there but dynamic would be very low.

Exactly. If you want to measure leakage power, shut the processor clocks
off (put the processor to sleep).

While Static and Short are pretty much constant? Or would Short also be directly
related to the amount of activity since it's determined by the slope of
the signal so if there's no activity, there's no direct current
situation since there's no switching done.

Yes, what you're calling "short" is "shoot-through" and can be considered
a component of the dynamic power. Though it's not directly related to any
capacitance, it walks like a duck.

So if we set the same (static becomes a constant) prescott at various
vcore (changes leakage right?), change the clockspeeds (changes
Dynamic), measure idle and load power dissipation, would we then be able
to calculate roughly the power used by Dynamic, Static, Short and
Leakage?

If you vary clock speed only, the Y-intercept (clock = 0) point would
indicate the leakage. At least at this level, forget "short" and
"static" power terms and include "static" and "leakage" in the static
term, and "dynamic" and "short" in the dynamic term:

Total = dynamic + static



--
Keith