In article , P2B
wrote:

I obtained a pair of Tualatin P3-S engineering samples, sSpec QEL8ES,
and tested them on an Asus P2B-DS using the 4 (long disused) multiplier
jumpers provided on the board.

I expected these processors would respond to changes in multiplier
setting (they do), but didn't know how the settings would be interpreted
since available documentation is from the P2 era and only goes to 8x -
whereas retail P3-S processors have fixed multipliers of 8.5x, 9.5x, or
10.5x. I assumed these would be supported, and hoped for some additional
more interesting numbers, but was disappointed.

My results were :

Jumper Setting(Decimal) Observed Multiplier Nominal Multiplier
0 4 2
1 9.5 4
2 8.5 3
3 9 5
4 NP 2.5
5 NP 4.5
6 NP 3.5
7 5.5 5.5
8 6 6
9 6.5 8
10 7 7
11 7.5 Reserved
12 8 6.5
13 NP 1.5
14 NP 7.5
15 4 2

NP means the processors did not post - not even at 66Mhz FSB, so I
assume the setting is not supported. Nominal Multiplier refers to
CPU:FSB clock ratios as documented for the P2.

If there's a pattern here, I'm not seeing it - even after various binary
sorts on the jumper setting. Seems plain odd.

As you can probably guess, I was hoping to clock these processors beyond
10.5x, but can't even get there. Any suggestions?

TIA

P2B

The only thing that comes to mind is, do you think the BSEL pins are
also inputs to selecting the multiplier ? Maybe the codes change as
a function of the perceived bus speed. Try the lowest multipliers and
ramp through the BSEL values, to see if the definition is changing at
all. That seems unnecessarily complicated, but you never know. Maybe
the higher multipler codes simply aren't supported in that stepping ?

There are four (dual purpose) signals on the Pentium that are sensed
on one of the edges of the RESET signal. One of them is called IGGNE.
No amount of searching on the Intel site would give any more information
on the table of values - the specs just say that the four signals
are sampled.

Good luck,
Paul