On Sat, 10 Apr 2004 13:01:39 -0700, "Jim" wrote:
Ok, one problem here is that the marketing hype leads the advertising people
to not quite state things correctly. Let's forget the details of that ad,
and talk as accurately as possible.
The CPU FSB is more correctly stated as 200MHz (actual), but since it
employs DDR technology, it's *effective* rate is 400MHz. The "400MHz"
number you see in the ad is actually misleading, the CPU FSB does NOT
physically *run* at 400MHz, it runs at 200MHz (that's what would show up on
a scope!), *but*, because the DDR technology it employs allows data to
travel BOTH on the up and down side of each cycle (per MHz), it's *behaving*
as if it data was traveling on ONE side of the cycle, but at 400MHz! Get
it? It's a marketing gimic, the CPU isn't actually *faster*, it's more
*efficient* (2x in fact) at the same speed of a 200MHz processor (1x) that
does NOT employ DDR technology.
The clock is just that. It's just a clock. It might run at 'just' 200
MHz, but it's _NOT_ the speed of the bus! The speed of the bus is
400MHz, and there's no marketing gimmick about that. That is indeed
the _speed_!
Now what purpose does the clock have?
It's like this: When data is transmitted on the FSB, data is
represented on the 72 pins (64 + ecc) out by voltage levels.
But as the data have to change to a new value, how do we know _when_
to read the data? When are all the leads ready, and the data correct?
That's where the clock comes in. The clock syncs the transfer. And
that is the _ONLY_ purpose of any clock. The clock tells _when_ the
data is supposed to be ready, and ok to read.
Now, you can sync on the clocks rising flank, or you can sync on the
falling flank. ... - Or, _both_!
AMD's FSB is the DEC Alpha EV6 protocol bus. And this happens to sync
on both rising and falling flanks.
So for a bus speed of 400MHz, - a 200MHz clock is _required_!
The data on the pins change 400 million times per second. That's the
_SPEED_ of bus! And that's only thing that matters, and marketing is
entirely 100% correct in stating that FSB speed is 400MHz.
That is not marketing hype or a gimmick.
I suppose I have to blame Intel marketing for everybody to be so damn
hung up on clockrates. - Hey, guys, - it's just a clock!
As for DDR ram, I don't know how it works, but I assume the actual
transfer is something similar to the EV6 bus. But there are more
complex things involved with memory access.
DDR speed only affects the bandwidth that memoryblocks can be
transferred with. An actual access is slower. A long chain of things
need to respond,
AMD did the same thing w/ their processors. Is an AMD
Athlon 2600+ actually running at 2.6GHz? No way, that's the hype, it's
actually 2.08GHz "on scope", AMD is merely claiming 2600 (2.6GHz) is the
*effective* performance compared to a 2.6GHz Intel CPU. Fact or fiction?
You decide.
It's not quite the same thing. But it's the same in the sense that the
clockrate is not the "speed" of any cpu. A clock is still just a
clock. The clock doesn't do the actual work.
Since Intel went for misleading the market with the P4, -
(The P4 is unique, since it's _less_ efficient per clockcycle than
preceding cpus, Pentium, PII, PIII. All other new generation cpus,
have always been more efficient per clockcycle than previous. That's a
natural outcome of an increased number of transistors. In the case of
the P4 and Prescott, their increased transistor counts are dedicated
to make it possible to run a higher clock. Not to do more work. This
is not good engineering. The P4 is engineered, intentionally, to run
at as high clock as possible. Certainly sacrificing performance! And
_THIS_ is indeed entirely marketing hype. A "gimic".)
, - AMD went for a 'rating' naming system instead. ...And so will
Intel shortly...
ancra
|