Hi,

I got an SVM enabled box, and was just trying out the extensions, when
I came across the following issues. I hope someone has the answers. :-)

The Pacifica Manual (Rev 3.01/May 2005), specifies that NP is optional
and implementation dependent. And that its availability can be
determined using CPUID: Fn8000_000A_EDX[bit_0]

As Pacifica became SVM and part of the mainline documenation
(Vol2/System Programming), Revision 3.11 (Dec 2005), section 15.24.12
"Detecting Nested Paging Support" continued to say "See appendix B,
page 91", which is obviously a bug in the doc, as there is no such
appendix.

As of Revision 3.12 (Sept. 2006), the same section says "see the AMD
CPUID Specification #24581". I searched for this doc, but there is no
#24581, though there is a #25481 titled "AMD CPUID Specification". I
check that document, and it says:

CPUID Fn8000_000A_EDX[31-0] are reserved. Not a single mention of
Nested Paging.

I ran a cpuid on the SVM machine:

eax in eax ebx ecx edx
80000001 00040ff2 0000090f 0000001d ebd3fbff
80000002 20444d41 6c687441 74286e6f 3620296d
80000003 72502034 7365636f 20726f73 30303033
..
..
8000000a 00000001 00000040 00000000 00000000

Going by the old Pacifica manual, the box does not have NP.
Nonetheless, I decided to go ahead and try out NP, and this is what I
recorded:

- When the guest CR0.PG is 0, NP_ENABLE (which enables NP) seems to
have no effect on the VM. However, according to the document, if NP is
enabled, any physical address generated within the guest must undergo
host-level page-translation, even if the guest paging is disabled.

- When the guest CR0.PG is 1, NP_ENABLE seems to be working. I set
H_CR3 (The host-level translation map for NP), to the physical address
of a page full of zeroes. I execute the VM, and it #VMEXIT's with
exitcode=0x400 (Nested Page Fault), exitinfo1 set to bit values as
expected, and exitinfo2 set to the fault address - as documented by
AMD.

Now, The old pacifica manual + the cpuid results + the behaviour in the
former case suggest that the box does not have NP. Whereas, the
ambiguous new manuals, the latter behavior suggest that the box does
have NP.

I tried searching AMD websites, forums, groups, etc., but no clue. Any
ideas, thoughts, suggestions as to what's up?

Thanks,
Vivek